ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<so-offish> How do I add an attributes to a cell, such that I can use Python to place them?
<so-offish> there's a bit of Python in Claire's presentation: if "ringosc" in cellinfo.attrs: -> how do I add an attribute like that?
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<so-offish> I figured out where that bit of code (in Claire's presentation) was from - it was from an ice40 example of floorplanning. I'm investigating now (this is just so if anyone looks at the log later)
<so-offish> The code to pass the attribute (from the Verilog, to the backend for use later, is here: https://github.com/gatecat/nextpnr-xilinx/blob/e69bbf9e32bf072918158d1de23da3f1c59fcf7d/ice40/examples/floorplan/floorplan.v)
<jix_> so-offish: that "(* ringosc *)" is the standard verilog syntax for an attribute, or are you asking how to add attributes that are not already in the source?
<so-offish> Honestly I didn't know that - I've only used attributes that had some effect in synthesis/routing, I had no idea you could just make your own attribute up and pass it to the back end (say for placement)
<so-offish> jix_ sorry forgot to add your name to the start
<so-offish> jix_ Like I didn't know you could do (* my_special_block *) and then do something with it. :)
<jix_> yeah I wasn't sure whether you knew and were asking for something different or not, which is why I did explicitly mention that this is standard syntax :)
<so-offish> jix_: Thank you for taking the time to clarify, I appreciate it. :)
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<so-offish> It was a good day for ECP5 ring oscillators.
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