<lkcl>
2112 // The ECP5 block RAMs operate in a non-intuitive manner.
<lkcl>
2113 // To connect both ports to the same set of memory cells, one port has to be attached
<lkcl>
2114 // 1:1 in address and data lines, while the other is offset (data + 18, address + 5).
<lkcl>
pasting that so it ends up in the irc logs for anyone else to find in future when searching for this same issue
<agg>
lkcl: thanks for the link, I think that's only for the slightly weird PDPW16KD primitive that exposes the 36-bit-wide ports, not the regular DP16KD which doesn't have that shift in address lines (but does have four byte-enables in the four LS bits, so 14 address bits per port)