ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<thezoq2> Is it possible to make yosys infer block rams when using "vector bit-select and part-select addressing" https://stackoverflow.com/questions/18067571/indexing-vectors-and-arrays-with#18068296
<thezoq2> I'm running it on some code which looks like
<tpb> Title: system verilog - Indexing vectors and arrays with +: - Stack Overflow (at stackoverflow.com)
<thezoq2> ```
<thezoq2> always @(posedge clk) begin
<thezoq2>      array[widx * 32 +: 32] = new_val;
<thezoq2>     out = array[ridx * 32+:32];
<thezoq2> end
<thezoq2> ```
<thezoq2> But it's not inferring it as block ram. Changing `array` to be a unopacked array works, but as I'm writing a compiler, it would be much more convenient for me to only work with packed arrays.
<gatecat> no, as far as I know the way the Yosys verilog frontend is written means that you have to use unpacked arrays if you want memory to be inferred
<thezoq2> Alright, thanks!
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