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<
Guest57>
i'm running `synth -top $::env(DESIGN_NAME) {*}$::env(SYNTH_ARGS)` and crapping out at the abc step
<
Guest57>
i've been trying to figure out how to recover the state that `synth -top $::env(DESIGN_NAME) {*}$::env(SYNTH_ARGS) -noabc` induces
<
Guest57>
so that i can restart the flow from just there
<
Guest57>
but there's so much state in context and design and env variables and etc
<
Guest57>
i tried `write_verilog/read_verilog` and `write_blif/read_blif` as checkpoints
<
Guest57>
but that doesn't work either
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