ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<cr1901> If I have a design with a single clock, and most of the design is gated by a clock-enable that only asserts every "n" cycles 1/2
<cr1901> Is there a way to tell nextpnr to treat the max freq of everything gated by that clock enable as clk_freq/n?
<cr1901> Use case- I want a 48MHz and 16MHz clock from a 12MHz input, but only have one PLL
<cr1901> So my idea was to generate the 48MHz clock directly and then clock en to simulate a 16MHz clock
<cr1901> Alternate solutions welcome, maybe I missed something about the ice40 PLL