ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<corecode> wouldn't you still have hold violations if your clock enable goes low after one 48MHz cycle?
<corecode> maybe you can use the output of a counter as a clock net and mark it as 16MHz?
<tnt> cr1901: no, nextpnr doesn't support that.
<corecode> hi tnt
<tnt> cr1901: I assume 48M is for usb ?
<tnt> corecode: o/
<tnt> cr1901: other option are (1) use 48 MHz from the HFOSC or (2) have the pll output both 96MHz and 48MHz and then use a couple of FF inside the FPGA to divide 96MHz into 16MHz (which won't be 50% duty cycle but doesn't matter)
<corecode> tnt: should be fairly close to 50% tho?
<tnt> Oh yeah right if you go from 96M it will be, I was still thinking of going direct 48M -> 16M.
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<cr1901> tnt: Why generate 96 as well as 48?
<cr1901> corecode: I can't think offhand of a simple example why there would be a hold violation; do you have an example in mind?
<cr1901> I _hate_ generating a clock from fabric like that, but if I don't have a choice I don't have a choice
<tnt> cr1901: huh, just if you want 50% duty cycle, yo ucan't start from 48 because dividing by 3 is not an even number.
<tnt> cr1901: And yeah, I hate it too, but on the up5k with a single not so flexible PLL, I had to use it as a last resort a few times.
<tnt> I make sure not to assume any kind of alignement and manually create a global buffer for it.
<tnt> cr1901: what's the application ?
<cr1901> Secret for now, mainly because I don't want to commit to anything rn :P, but the 48MHz domain isn't for USB actually
<cr1901> well, at least not exclusively
<cr1901> I need a fast domain to emulate a latch
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