<klange>
Something I've done in my graphics stack, or something that changed in VBox, is annoying me... I seem to not get the initial message I used to get to switch the display mode... I think it might be from modesetting in my bootloader.
<klange>
But it's annoying, because I start up in, like, 1024x768 because that's a suitable resolution VESA advertises and then... it just sits there.
<klange>
Used to be I would have a pending message from the host-guest interface and it would snap to the right resolution from, like, a mouse interrupt.
<klange>
I should update to the newer interface, I wrote this against the legacy one and it nags in the log every time.
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<klys_>
I've been asking about something in #qemu just it seems mebby nobody's there
<bslsk05>
github.com: qemu/qdev-device-use.txt at master · qemu/qemu · GitHub
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<klys_>
and it looks like that's on gitlab too
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<geist>
klys_: yeah the qemu channel doesnt seem that busy does it
<moon-child>
optimization I never knew I wanted: compiler should know to convert memmove(x, x + i, 64 - i) into memmove_asc_small(...)
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<geist>
i've been fighting addresses-of-fields-of-packed-structs
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<geist>
compiler really really dissuades you from doing that
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<pounce>
klys_: #qemu is on oftc, libera channel isn't very busy
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<klys_>
pounce, yeah I was doing oftc #qemu today
<pounce>
oh sorry i haven't been in there long bouncer died
<klys_>
my nick there is klysmo
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<geist>
i forget, whoever has dealt with pci before, is it incredibly important to read pci config registers in the right width?
<geist>
i can imagine writing it almost certainly is
<zid>
it says it is
<zid>
whether the device controllers give a shit idk
<geist>
yah i just replaced my routine that reads pci config space in a byte at a time with one that reads in all the fields in the correct width
<zid>
I think you can combine on the 16s
<zid>
err that is, two 8s
<geist>
i'm guessing it's basically up to the device, but the spec says the device can be dumb and not handle sub field read/writes
<geist>
and of course emulators probably generally speaking work fine with bytewise access
<zid>
matching the size defo seems safest, and it's not performance or code density critical so whatever
<geist>
oh totally
<geist>
second question: i assume big endian machines have to deal with the implicit LE order? or... maybe they dont, because it's assumed you access fields with the correct width
<zid>
hmm?
<zid>
oh hmm
<zid>
I guess if it's a 16bit 'char' for that field, there's no endian
<zid>
but I don't think that's the case
<zid>
I think it's byte addressable
<zid>
and whether it allows combining up to 16/32/64/etc is up to the device
<geist>
yah and if so then what's the endian order a pci config space?
<geist>
i can imagine if the spec says 'the fields must be accessed in native sizes' then it can also appropriate swizzle based on the host cpu endianness
<zid>
so if you read anything using wide reads it's going to be backwards on BE
<geist>
since the pci bus controller presumably knows that
<zid>
it's not swizzled
<geist>
and if so that may be precisely why you're supposed to access them inthe native size
<zid>
random quote from google cache of osdev, good job google
<zid>
"PCI devices are inherently little-endian, meaning all multiple byte fields have the least significant values at the lower addresses. This requires a big-endian processor, such as a Power PC, to perform the proper byte-swapping of data read from or written to the PCI device, including any accesses to the Configuration Address Space. "
<geist>
word.
<geist>
intel definitely had their hand in it, so i guess at that point in time they pushed for LE
<zid>
LE makes the most sense anyway, BE can die
<geist>
i can't easily test it anyway since none of the BE arches i have ported to have a machine with PCI i can test on
<geist>
unless i make a BE build of ARM or something
<geist>
which, meh.
<zid>
At any case, it's just 'ram' which.. becomes even more apparent when you use pci-e
<zid>
where it's memory mapped but still identical
<zid>
so you'll need to le_to_host it all if you do multi-byte reads
<geist>
yah or you can consider it a big pile of MMIO registers that the device exports
<geist>
i have seen some situations where the bus swizzles the data to the device based on the access width, since it knows the endian of the machine
<geist>
i think there was some of that on playstation 3 for example, since the PPC/SPU cpus were big endian and the NV47 GPU was mostly little endian
<zid>
I do all my reads as 32bit
<zid>
then shift them around depending on the 'offset' I think
<geist>
lots of swizzling in the textures and whatnot
<zid>
oh because register offset must be xxxxxx00 maybe
<zid>
so infact I had it backwards, and you *must* do 32bit reads?
<zid>
The PCI pdf probably says all this, but I don't have one
<geist>
hmm, for type 1 accesses, yeah i guess that's right?
<geist>
ie, via the in/out access method?
<zid>
yea, idk if you *can't* do that, for pci, it isn't memory mapped until pci-e
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<geist>
but writes, do you have to do a RMW if you want to just piddle with 8 bits? (I haven't iomplemented that for type 1 accesses)
<zid>
I imagine so? There address selection is agnostic to reads or writes
<zid>
s/There/the
<zid>
You're still doing out32(CONFIG_ADDR, ...); regardless of reading or writing
<zid>
and that's the part that masks the bottom 2 bits as 0
<zid>
so you can only select dword aligned addresses, so a rmw might be needed (or you just keep a local copy and keep it in sync, but you're not an idiot so idk why I typed this bit)
<zid>
I don't have code for it, the only writes I do are 32bit for the BARs
<geist>
oh i dunno, i mean i could look this up
<geist>
but it seems like a nice topic
<zid>
oh the command reg is 16 I do touch that.. I wonder what's next to it..
<zid>
ah, status
<zid>
I imagine writing to those doesn't matter
<geist>
but yeah looks like the type 1 config accessor is definitely 32bits at a time, in aligned 32bits so
<zid>
32bit write to BAR, 32bit write to status | command
<geist>
yah possibly they carefully arranged it such that bits you write to are always shared with bytes that dont latch on write
<geist>
cleeeever
<zid>
The other one you might wanna mess with is the bridge control | int pin | int line one
<geist>
or a bunch of 8 bit fields you want to write all at once
<geist>
ah also notice the capabilities pointer is not shared with anything
<zid>
so just treat that as one big field I guess
<zid>
bridge_pin_line
<geist>
though i guess yo never write to that
<geist>
so i gues that begs the question: with pci-e are you always supposed to read the ECAM in 32bit offsets
<geist>
or more importantly: write to it in units of 32bits
<geist>
probably no, but it does beg the question as to what happens if you have a PCI device on a PCI-to-PCIE bridge and you access its config in 8 bit intervals
<zid>
I think pci-e is flexibable because the bus acts like memory and they have to support 'the pci-e bus'
<geist>
and it was previously never accessable that way
<zid>
hmm yea that's a good one
<zid>
I wonder if the bridge has to split/combing
<geist>
right
<zid>
orr the pci-e bridge just has to be treated like a bridge, and you have to use its interface to issue pci writes, and it's specified the same way as pci was
<zid>
like, there's just an mmio reg on the pci-e device that is the bridge, which implements 0xCF8 and 0xCFC or whatever, and says 'do it like pci'
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<zid>
found a random TI pci-e to pci bridge chip's doc, it just says "this device acts like a pci to pci bridge type 1"
<zid>
And I think the spec for that says there's a register that's 0 if 16bit io is supported, 1 if 32bit
<klange>
I just want to say that the Shell Command Language specification in POSIX is by far the worst language specification it has ever been displeasure to place in front of my eye balls.
<zid>
geist: made in abyss s2 (3rd part, with the movie) has preview visuals being released :o it's coomiiing
<bslsk05>
pubs.opengroup.org: Shell Command Language
<klange>
it is _the_ spec for sh, and it is an astounding feat of non-linear storytelling
<moon-child>
I just saw
<moon-child>
somebody implementing the visitor pattern. In _C_
<zid>
I don't even know what that is, my soul is untarnished
<moon-child>
zid: I envy you
<zid>
The wikipedia example is like "A naive way would be *perfectly reasonable way to do it*"
<zid>
as though functions can't exist
<klange>
I do know what that is, but I do not feel unnerved.
<kazinsal>
one of those enterprise programming paradigms where everything is a ClassInitiatorProviderFactoryFactory
<zid>
yea it definitely looks like "We don't understand how to write code in the first place, so this is one of the hacks we came up with"
<moon-child>
I mean, it kinda makes sense given you're already using java. In c I have no idea why you would want it
<zid>
Moving operations into visitor classes is beneficial when
<zid>
many unrelated operations on an object structure are required,
<zid>
Also known as "functions accepting pointers"
<zid>
"new operations need to be added frequently" also known as "functions accepting pointers"
<zid>
etc
<klange>
Ignore the class aspect for a moment; is the visitor pattern not evident in functions like qsort? It is about implementing algorithms in ways which may accept various objects, and about implementing the type-specific functionality without extending the particular types.
<kazinsal>
it makes sense when your productivity is purely judged by lines of code
<moon-child>
I don't think using function pointers constitutes visitor pattern. It's the weird inversion of control and the large amounts of boilerplate
<zid>
qsort being well known to be absolutely awful
<kazinsal>
when you need 50 lines of boilerplate per each actual operation line...
<zid>
"A drawback to this pattern, however, is that it makes extensions to the class hierarchy more difficult, as new classes typically require a new visit method to be added to each visitor. "
<zid>
It'd be like if you had to add a qsort comparitor function for every single type, by the sounds of it
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<zid>
as soon as you started using qsort anywhere in your code
<klange>
No, just for anything that would be sortable.
<zid>
which is anything, potentially
<klange>
The alternative to the visitor pattern is to have common class functions - eg. interfaces.
<moon-child>
klange: qsort isn't ISortable, it's parametric polymorphism. It's just that they both look like void* in c
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<kazinsal>
dog bless the language that forces us all to double-check our every move
<zid>
If my pointers ever look like `void* ` you can shoot me btw
<moon-child>
qsort :: [a] -> (a -> int) -> [a]
<kazinsal>
if I need something resembling polymorphism in C I use anonymous member structs with plan9-extensions
<zid>
okay I found an easy code example for it, it looks *exactly* like adding a common interface to a set of objects
<klange>
tagged unions
<zid>
but with a stupid name
<zid>
and an extra function to call all of them
<klange>
zid: The visitor pattern is, rather literally, implementing a common interface separately from the classes.
<kazinsal>
eg. all of my interface types start with an anonymous net_generic_t; so you can send a specific interface to any function that takes a net_generic_t and also so any change to net_generic_t automatically propagates to each interface struct
<klange>
For example, say you want to write a JSON serializer. You _could_ add an interface, an "IJSONSerializeable" or whatever, and implement the method across all the classes you want to serialize...
<zid>
I don't know what any of that means ^
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<klange>
The visitor pattern is for hot-patching an interface onto things that didn't implement it.
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<zid>
I mean, that just sounds.. completely normal?
<zid>
If I want to know about how many otters my 'class' (read: .c file) has captured, I add a function to tell me
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<moon-child>
zid: open-world assumption
<zid>
pardun
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<kingoffrance>
re: visitor pattern wikipedia emphasizes double dispatch. https://en.wikipedia.org/wiki/Double_dispatch there is a silly ruby example there. all that is just to say: i think if you had <thing to do, e.g. qsort()> <comparison function> one more layer of indirection on top of qsort, that would be closer
<bslsk05>
en.wikipedia.org: Double dispatch - Wikipedia
<kingoffrance>
not advocating either way, just seems one level above qsort if one was to make that comparison (no pun)
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<kingoffrance>
or, alternately, qsort invoked with a chain of comparison functions (to break ties, something beyond single level, single comparison function). I believe that would also be closer
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<immibis>
Mutabah: yes. see also: how to make artificial general intelligence (1) recognize MNIST digits (2) make the rest of the (fucking) intelligence
* Mutabah
is away (Sleep)
<immibis>
i'm pretty sure the instructions have to contain the word "fucking"
<immibis>
how to write any program: (1) write hello world (2) write the rest of the (fucking) program
<immibis>
i think in osdev the (1) is an GDT and IDT
<geist>
haha
<rustyy>
TIL about queued spinlocks, i feel pretty good =)
<kazinsal>
if your OS doesn't spontaneously crash after 24 hours of uptime, you can move onto the "write the rest of the fucking operating system" stage
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<klange>
24 hours is easy; the real benchmark is when you've forgotten a VM running on another workspace for three weeks and you find the clock still ticking.
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<kazinsal>
and it's still switching packets like a champ
<geist>
rustyy: ooooh
<geist>
do tell!
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<kingoffrance>
thats almost Schrödinger ...if a server is buried in a wall and people forgot it exists, is it still routing packets? have to open it up and see
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<geist>
so easy with wifi too. you can easily forget you had some raspberry pi on the network somewhere
<geist>
or one that's embedded in some other thing
* gog
embeds a rasbperry pi into herself
<gog>
am borg
* gog
assimilates the channel
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<vdamewood>
We are dyslexic of Borg. Prepare to have your ass laminated.
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