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<ZetItUp>
with PE file's, it says it need to be put at a location X in virtual address space, do i need to reserve some space which is only for PE files, or am i overthinking it and it is fine to put it at any location, just add it to the image base address?
<ZetItUp>
im just wondering about, what if two or more files wants the same virtual address
<clever>
ZetItUp: if runtime relocation data is included, the dynamic linker can patch the binary as it moves it to a different address
<moon-child>
ZetItUp: each process gets its own personal virtual address space
<clever>
windows will also cache the patched versions somewhere, to speed that up
<clever>
and yeah, each process gets its own private virtual space, so a collision can only happen between 2 dynamic libraries loaded by the same process
<ZetItUp>
ooh that makes sense
<clever>
but that relocation patching can prevent sharing of the read-only chunks of a .dll
<clever>
so the system winds up having to store 2 copies of the same .text
<clever>
in ram
<ZetItUp>
yeah i was thinking of having some kind of lookup table in memory which has the name and at what address the file is located at, not sure if that would be a good design thou
<clever>
cygwin will also track what virtual address it has used in every dynamic library it builds
<clever>
and ensure there is no collisions between any lib it produces
<clever>
that then entirely eliminates the need to do runtime relocation
<clever>
but thats only really feasible on a 64bit system
<ZetItUp>
i wonder if that would cause any errors in multi-threading though, if like several processes uses the same memory location for a library
<ZetItUp>
be careful with locks i guess hehe
<moon-child>
yeah, starting up a process is rare/slow enough that even if you go for fine-grained concurrency, lock on cache miss is fine
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<gorgonical>
That's the feeling we're all looking for -- the "holy shit it works!" moment. After like four days I got it lol
<AmyMalik>
idk, i'm just looking for the feeling of soft fuzziness
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<gorgonical>
I have that feeling too from my wool socks
<AmyMalik>
I mean like, a feeling like "I'm safe here"
<Affliction>
geist: I'd expect it would free the bus to allow the controller to talk to another bank group or rank? Could make things faster that way.
<Affliction>
Assuming DDR5's addressing works the same way, maybe I should actually look into how it works at some point
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<geist>
hmm, yeah
<geist>
re: the overlapping zeros
<geist>
cpus definitely know about writing zeros optimally, so it should be easy to wire up
<geist>
actually wikipedia says the DDR5 thing is even more intersting. there are something like 256 registers on the chip, and you can tell it to write the contents of one of them
<clever>
i saw something about that in the arm docs
<geist>
so presumably that means you can fill in whatever bit pattern you want ahead of time
<geist>
clever: yah ARM and now AMD explicitly have zeroing instructions, thouh i have no doubt that other arches already have ways to sense that a cache line is full of zeros and bypass certain steps
<geist>
it would be easy enough to at least sense a zeroed cache line
<clever>
what did arm call it again?
<geist>
the arm64 instruction is `dc zva`
<geist>
dunno if they back ported it to arm32, came along in armv8
<geist>
AMD now has `clzero`
<clever>
ah
<clever>
that feels different from what i saw before
<geist>
that's explicit zeros at least. i wouldn't be surprised if they sense a zero automatically in some cases. especially x86 where you have a rep stos you can fairly easily detect a zeroing operation
<geist>
the big difference i think with dc zva and clzero is they explicitly write thru the cache
<clever>
but i did stumble upon the vector opcodes in the armv7 docs, i should look into that later
* clever
checks something
<clever>
one of the rpi engineers claimed that NEON should be faster then the VPU vector stuff (but my math shows 1.5 mill/sec vs 6.6 mill/sec)
<clever>
but they also appear to be mixing up the different vector things the rpi can do (vpu vs 3d core)
<clever>
and i dont know how well optimized the gnuradio neon code is
<clever>
i feel like some hand-optimized neon asm would give a more fair comparison of the 2
<geist>
yeah
<clever>
because it feels wrong, that a 500mhz single core with vector extensions
<clever>
can out-compute a cortex-a72? in aarch64 mode at 1.8ghz
<clever>
but also, that 1.5 million sample/sec, was running the whole gnuradio pipeline, and using float based math
<clever>
while the 6.6 million/sec, is based on profiling 10k runs of the function, computing cycle cost, and dividing with clock rate, and using int16 math!
<clever>
and assumes the L1 cache will play ball
<clever>
so i'm both comparing vectors of floats to vectors of int16, while also stripping a large amount of the complex problem out
<clever>
but sleep time first
<clever>
geist: oh, and one last thing, what are your thoughts on getting ext4 write support? push that off until later or try to include it in the same pr?
<geist>
well, both. getting write is great, but also breaking things into a series of CLs would be great
<geist>
uber CLs are always hard to deal with
<clever>
and i cant cheat like grub does, modifying only the data blocks
<clever>
because my intended goal requires creating files where the name isnt known ahead of time
<geist>
it's a *substantial* amount of engineering
<geist>
hence why getting things in as pieces is helpful
<clever>
basically, i want to boot a file on a random rpi, and then dump everything of use (otp, maskrom), to a file on the sd card, named after the serial#
<clever>
extracting hex out of the uart and turning it back into binary is a pain
<clever>
creating binary directly on the card would make it so much simpler
<clever>
i can think of several layers that would be involved, 1: selecting free blocks, 2: creating the extent tree to reference the data blocks, 3: updating the directory listings, 4: updating the free space maps
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* clever
heads off to bed
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<HeTo>
via rep stos*, x86 has had instructions for filling the memory with a certain bit pattern since the beginning
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<Maka_Albarn>
anyone know what's up with osdev. org?
<klange>
it's definitely quite unhappy
<ThinkT510>
timed out for me
<Maka_Albarn>
same
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<junon>
Yeah :(
<junon>
Who hosts it?
<klange>
It's all a single Linode instance run by chase [who is not here and does not generally do IRC these days]
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<Ermine>
Uh oh
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<ksp>
Hello
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<ksp>
Epic ping failure
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<kingoffrance>
if they pinged back, youd know their ip is real </sarcastic security>
<ksp>
Yeah true
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<ksp>
RISC-V phone running FreeBSD based OS 🗿
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<sikki>
Anyone know how to load a custom kernel(as simple as writing Hello World to UART) at the addres other than default(0x80000
<sikki>
on raspberry pi 4
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<sikki>
I have simple kernel which can write hello world to UART only if it was loaded at 0x80000, it doesn't run at other addresses
<sikki>
but standard kernel is able to run at 0x200000, how is that possible?
<sikki>
I have also tried changing the load address in the linker, but still, it only runs if both address(in linker and config.txt on rpi) are 0x80000. How can I load it at different addresses.
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<clever>
sikki: there is a config.txt flag to set the load address
<Maka_Albarn>
can anyone tell me how to handle the fact that the APIC accepts interrupt vectors ox10-0x1F when those are Intel exceptions?
<clever>
sikki: you also need to tell the linker what address you will be loading at, or write pure PIC asm
<geist>
and/or you could write some PIC asm at the very start of your kernel that relocates itself via copying to final location and then branching into it
<geist>
it's tricky to do the first time, but quite simple once you understand it
<chibill[m]>
is the wiki acting really weird for anyone else? It keeps every now and then hanging when changing what page I am on then timing out.
<sikki>
I have wrote the load address in the linker script at the start and also in kernel_address in config.txt
<sikki>
@clever, can you elaborate further on kenrel relocating itself? or point me towards the resources to learn more about it.
<geist>
chibill[m]: i think it's been down most of the day
<geist>
suprised you're getting anything at all
<chibill[m]>
It works on and off right now.
<geist>
yah wont even load for me
<chibill[m]>
I am actually working on writing the code for my Homebrew CPU / Computer. Using what I learned from OS Dev to make the design for some of the hardware like the screen.
<clever>
sikki: option 1, write your kernel to be 100% PC-relative, so it doesnt care about whre its loaded
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<clever>
sikki: option 2, use some PC-relative code to copy it to the right address on startup
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<clever>
sikki: option 3 (what most things do), use some PC-relative code to configure the MMU, so it looks like it was at the right address the whole time, without moving it
<ksp>
Oh hello
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<sikki>
@clever, for option 1, how can it be done? Even if I don't sepecify any address in the linker script, it doesn't run at address other than 0x80000. Can option 1 work for raspberry pi 4, it's default address is 0x80000 for 64 bit kernels.
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<clever>
sikki: you need to only use opcodes that are pc-relative
<Maka_Albarn>
repeat question: how do you remap irq's 0-7 with the apic?
<Maka_Albarn>
make that 0-15.
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<ksp>
Hello
<geist>
Maka_Albarn: the ioapic? I think the base register is just in there somewhere
<geist>
ksp: hola
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<kazinsal>
should put that on my to-do list for vacation coding
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<geist>
i assume the bios maps the ioapic to somewhere reasonable at boot, never looked into it
<geist>
also.. now that i think about it it may be that you can configure each vector independently. now that i remember it i think zircon dynamically assigns them as drivers claim the vectors
<geist>
so they tend to get packed in, allocated sequentially by which driver claims first
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