_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tpw_rules> does dolu1990 hang around here?
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<tnt> tpw_rules: nope.
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<somlo> _florent_: is there a way to control where in register space the LiteScopeAnalyzer is placed? I'm trying to add it to an existing design for some debugging, and it's shifted my entire register map up by 0x800 by going in first, before `ctrl_reset`
<somlo> be nice if I could avoid having to redo my entire DTS to accomodate it :)
<ysionneau> also, on the other hand, it could be nice to be able to auto-generate the dts, a bit like the csr.csv is generated
<ysionneau> somlo: maybe you can override the csr_map property of SoCCore ?
<ysionneau> or maybe the csr_reserved_csrs
<somlo> rocket support for litex_json2dts is "on the road map", but for now I'm doing (rare) manual edits when the auto-generated map changes :)
<somlo> besides, I may not actually care if the blobs being loaded match the DTB, for the purpose of looking at the litescope generated data -- so NVM, I'm "un-asking" the question :P