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<Guest3813>
hello, sorry to bother you guys again, is there a good reason why litedram will work in simulation and not on real hardware?
<Guest3813>
I'm using it standalone and i tried both the native and the wishbone interface for data. I can initialise fine and write data but i'm only reading back zeros on hardware
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<Guest3813>
For anyone in a similar situation looking at the chatlogs, I figured that at least one problem is that i haven't implemented the software read/write leveling ( I use DDR3 )
<ysionneau>
if I want for instance to do request the serial pins
<ysionneau>
-do
<Guest3813>
I don't know much about the project in general but i would assume if you are running linux they should be exposed to the kernel
<Guest3813>
btw I'm using an orangecrab too :)
<ysionneau>
I mean, I am writing a target file and I want to do something like platform.request("serial")
<ysionneau>
I am writing another SoC to run on OrangeCrab
<Guest3813>
oh sorry you lost me then, i don't know
<Hoernchen>
well just copy the approach from the orangecrab feather soc? platform.add_extension(orangecrab.feather_serial), self.platform.request("serial") ?
<ysionneau>
oh, I didn't know about the add_extension, thanks!
<ysionneau>
where did you find the feather soc? it's not in my litex_boards
<Hoernchen>
gtihub search
<Hoernchen>
i'm always just using the gh search to figure out how something is being used
<ysionneau>
good idea thanks
<Guest3813>
I finally got litedram to work!
<Guest3813>
i think i got away without read leveling by setting cmd_delay to a low value (0) inside the .yml config and also i had forgotten to switch to hardware control with sdram_dfii_control_write