<Hoernchen_>
it appears to work on 8.2, but eth is apparently a bit flaky, and pings get lost
<Hoernchen_>
it is hard to tell why tho, it might just be general timing issues when building the bitstream
<Hammdist>
timing issues sound like they would affect all versions equally, if that were the case. dunno what it might be though
<Hoernchen_>
yeah but the problem is that no one is building images for those boards and there have been years of changes
<Hoernchen_>
the problem is that you can't define false paths that should be ignored so there have always been timing errors, and I don't know if any of that was ever better/worse or matters at all
<Hammdist>
hm. well my design passes timing without errors in nextpnr at speed grade 6 ... I haven't got around to testing it on the colorlight yet, I have only tested it on the lattice versa board and it seemed to work there but there was a strange problem very similar to what you describe (corrupt ethernet packets, i.e., packet loss in the end)
<Hoernchen_>
changing the timing parameter didn't improve anything
<Hoernchen_>
..but flooding basically "improves" the packet flow
<Hammdist>
so I should try to source the v7 boards, if possible in 2023 q4
<Hoernchen_>
one is like 15 bucks so just give it a try
<Hoernchen_>
but if your design passes timing on the versa.. well, just check it for the colorlight, and if it passes timing it might just work
<Hoernchen_>
tho if you are seeing the same issues on the versa i guess something might be broken after all
<Hammdist>
yeah I put the same design that passes at speed grade 6 on a 5g part ... it can't be the timing
<Hammdist>
I tried to determine whether the errors in ethernet are rx or tx, and found out that, surprisingly, they are both, though rx is affected to a significantly greater extent than tx. I don't know what more to try. I suspect the lattice ddrs simply can't do rgmii. I will probably be switching to xilinx next - maybe that will work better.