04:15 <jevinskie[m]> <_florent_> "cr1901: But you'll only easily..." <- I’ve been thinking about a yosys pass to flush up all the monitored signals to a higher level port

07:25 <_florent_> jevinskie[m]: This could be very convenient indeed for modules that can be synthesized with Yosys. This would provide an intermediate state between current possibilities and vendor tools. For designs that can be fully synthesized with Yosys, this could even be almost equivalent to vendor tools.