_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tpw_rules> is there an offset in litescope between scope_trig and the actual triggering event? it's my first time using it and i see like 16 cycles between scope_trig being asserted and the condition i described on the command line
<tpw_rules> which is suspiciously similar to the default trigger_depth
<cr1901> yes there is an offset (at least in older versions), the idea being you may want to see stuff before the trigger. It is configurable. However, Idr offhand if "trigger_depth" is the parameter that controls number of samples to keep before trigger.
<tpw_rules> yes, i understand there's an offset between the start of the capture and the start of the trigger
<tpw_rules> but i would expect that's why there's the scope_trig signal to tell where the trigger occurred. there seems to be an offset there
<cr1901> oh hmmm, sorry, I wouldn't expect an offset there either. Not sure what's going on
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<minute> is UsbOhciWishbone integration broken? on a fresh setup, i get `Error: Could not find or load main class spinal.lib.com.usb.ohci.UsbOhciWishbone`
<minute> `sbt run` in "pythondata-misc-usb_ohci/pythondata_misc_usb_ohci/verilog/ext/SpinalHDL" gives "No main class detected."
<minute> aha, it works if i set "project lib" first in the sbt console
<minute> another error: Error: Option --phy-frequency expects a number but was given '48000000.0'
<minute> ah, and that appears to be the root of the problem
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