_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<somlo> MoeIcenowy: did you ever get the sdcard working when *not* in spi-sdcard mode (on your stlv7325 "classic" board, that is)?
<somlo> mine only works in spi mode so far
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<MoeIcenowy> somlo: mine seem to work
<MoeIcenowy> somlo: but it's weeks ago
<MoeIcenowy> and I previously have broken litesdcard experience on tangnano20k
<MoeIcenowy> so maybe litesdcard regressed?
<MoeIcenowy> somlo: BTW the document says SD card pinout is changed on v2
<MoeIcenowy> (in addition I am thinking about getting a FMC-equipped STLV7325 v2 to test FMC adapters by CHIPS Alliance
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<cr1901> IIRC, litesdcard uses parts of the SD spec that not all cards are required to implement (UHS 1)
<tnt> How does one get access to the clock domain of the current block ? Like i want a PulseSynchronizer from sys to XXX (with XXX being whatever CD the block is in) ?
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<somlo> sdcard works great on e.g. digilent-nexys-video, lambdaconcept-ecpix5, and a bunch more boards I have sitting around
<somlo> and since it works fine on the stlnv7325-v2 in *SPI mode*, at least those pins are connected according to the document I got from the designer :)
<somlo> in SD mode there are an additional 2 pins involved (data[1] and data[2]), which might be wrong, or reversed, or who knows -- since if i try building bitstream with a proper SD-mode sdcard block, it doesn't work on that board
<somlo> same migen source, same physical sdcard, so everything else is identical on both "sides" of the FPGA <-> pads link :)
<Flea86> smolo: Does lowering the sd clock rate improve matters?
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