_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<somlo> before I commit, I wanted to ask if there's an easy way to log an error from the args_read() method (lines 78 and 82 in the github link above)
<somlo> i.e., I want a warning or error logged if the requested number of CPU cores is anything other than [1, 2, 4, 8] -- the pre-elaborated verilog sub-variants in pythondata-cpu-rocket
<somlo> ditto for memory-bus widths (1x, 2x, 4x, and 8x 64bit)
<somlo> no other cpu model throws errors or warnings anywhere under litex/soc/cores/cpu/*, so I had no previous examples available for cargo-culting :D
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<droiddbot> Hey
<droiddbot> Hey
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<cmmon> Hey
<cmmon> I am new to litex
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<bl0x> o/
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