<MoeIcenowy>
cr1901: previously we didn't properly enable H because of some weirdness of Rocket
<cr1901>
I didn't even know "H" was an extension
* cr1901
lost count
<MoeIcenowy>
Hypervisor
<cr1901>
ahhhhh
<cr1901>
RISCV IMAFDCOMGWTFBBQ
<MoeIcenowy>
cr1901: you are out of date
<cr1901>
Oh?
<MoeIcenowy>
now it's RV64IMAFDCVSUZicsrZifenceiSs1p12
<MoeIcenowy>
like this
<cr1901>
It's missing the L spec
<cr1901>
:P
<cr1901>
(Also, My God we've run of out alphabet, haven't we?)
<MoeIcenowy>
new single-letter extension now rarely appear
<MoeIcenowy>
cr1901: yes
<MoeIcenowy>
and it tend to divide single letter ones to multiple multi letter ones
<MoeIcenowy>
e.g. original B is now ZbaZbbZbs ...
<cr1901>
Well, L spec is Decimal Floating Point, which I'm actually curious about just because it would be interesting. But there hasn't been movement on it AFAIK
<cr1901>
ahhhh
<cr1901>
Is the single letter "B" still used if the entirity of "ZbaZbbZb..." is implemented?
<MoeIcenowy>
well I dont know...
<MoeIcenowy>
Waterman says there's now no B extension
<MoeIcenowy>
SiFive has some B option
<cr1901>
ahhh, I remember when Claire Wolf (yosys dev) was working on the B extension. Idk if she still is, but you're right that I'm out of date.
<MoeIcenowy>
but it does not even contain Zbs
<MoeIcenowy>
it's only ZbaZbb
<MoeIcenowy>
cr1901: well in RV context maybe you should better call her picorv32 dev ;-)
<cr1901>
Hehehe fair enough :D!
<MoeIcenowy>
I do admire picorv32 and it inspired me when I was doing my homework in college on Computer Orgnization
<cr1901>
There was no RV when I took Comp Arch, so we made our own bare minimum RISC CPU in Verilog w/ custom insns.
<MoeIcenowy>
(well I did a very rubbish rv32i (even without Zicsr) core then, and did run something produced by GCC
<cr1901>
I have a RV32 core that's "mostly" ready, but I need to write the microcode for it (size optimized!). I'll get it merged into LiteX after that
<MoeIcenowy>
oh I want to see it ;-)
<MoeIcenowy>
I am always curious about microcoding, but I haven't really understood it
<MoeIcenowy>
_florent_: could main ram be used as DMA destination?
<MoeIcenowy>
GW2A-18 is not very rich of BRAM
<MoeIcenowy>
but I got the 8MB SDRAM on GW2AR-18C running
<MoeIcenowy>
somlo: btw Zenithal says Zk* Zb* are heavy of size
<tpb>
Title: William D. Jones: "For those who have no idea how microcoded CPUs wo…" - Mastodon (at mastodon.social)
<MoeIcenowy>
ah thanks
<cr1901>
Like pico/femtorv32, my RV core isn't fast. It's meant to be small. Microcoding it is intended to abuse block RAMs as a way to use less FPGA logic
<MoeIcenowy>
cr1901: or maybe it can use LUTRAM?
<cr1901>
Yes, that's also an option for non-ice40 FPGAs
<cr1901>
My scripts for testing size were meant for the worst case of ice40 (no LUTRAM)
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<MoeIcenowy>
_florent_: GW2A-18 seems to be very short on BRAM, when I use standard vexriscv + sdcard, I got `The number(49) of BSRAM in the design exceeds the resource limit(46) of current device.`
<MoeIcenowy>
maybe I should look at GowinSynthesis result
<somlo>
All I wish for is yosys/nextpnr for whatever FPGA is on the Alveo boards ;P
<somlo>
if only I didn't have to work for a living, I could dedicate the next 10 years to making it happen :D
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<MoeIcenowy>
well litesdcard seems to use 18 BSRAMs
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