_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tpw_rules> how do SerWB and SerDes in liteiclink relate to each other?
<tpw_rules> is it possible to connect SerWB to the SerDes? does that then require only two links? (tx and rx)?
<tpw_rules> the testbench makes it look like that is the case but the verbiage in the readme is a bit confusing
<tpw_rules> the examples make it look like that is not the case..
<tpw_rules> why is there a clock between the two devices anyway?
<tpw_rules> i think the ecp5 serdes at least can do clock recovery?
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