_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<animatrix> hello
<animatrix> i'm trying to build verilog rtl of litedram for arty
<animatrix> i'm not sure what to do though, can anyone help me out ?
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<animatrix> please help me out
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<_florent_> and do litedram_gen arty.yml
<_florent_> then customize the user ports to your need: https://github.com/enjoy-digital/litedram/blob/master/examples/arty.yml#L35-L52
<_florent_> and re-run
<animatrix> yeah i found an issue with some data of how to use
<animatrix> btw
<animatrix> why does litedram use ISERDES in networking mode and not memory mode
<animatrix> i see people reading the input dqs strobe and using that as a clock to the DQ iserdes but that doesn't seem to be what's going on here
<animatrix> also memory mode is only capable of 1:4 and not 1:8 like networking, i'm not sure what the compromises are of using either in this situation
<animatrix> 2. I tried simulating litedram for 100us with a ddr3 model, i see a lot of 'X' on the address lines. The controller keeps repeating a precharge all and doesn't do the init sequence and init_done never becomes true.
<tpb> Title: image — ImgBB (at ibb.co)
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<animatrix> i'm unable to get init_done to go high :(, all the simulation shows is PRE command followed by refresh command every 7-8us
<animatrix> i've simulated it for around 200us and no dice
<animatrix> am i doing something wrong ?  I thought once i let go of the reset the controller should start initializing the system
<animatrix> mode register programming and all that
<animatrix> nothing seems to be going on
<animatrix> my testbench is fairly simple, 200Mhz clock. hold reset for the first 1000ns and let go.
<animatrix> using vivado so all the xilinx modules can be simulated too
<animatrix> is there a discord or something for litex ?
<zyp> this is the something, as far as I'm aware :)
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