12:57 <xdarklight> hexdump0815: I found this: https://github.com/khadas/linux/commit/d1d98f2ed8c83eb42af8880ed8e206aa402dd70a#diff-c5aaf54323ef93777c5083de37f933058ea8d0af79a1941e0b5a0667dc0f89b3

12:58 <xdarklight> hexdump0815: why would one need to poke a SAR ADC register for the MPLL clocks? very strange...

12:58 <xdarklight> hexdump0815: can you dump the SAR ADC clock registers from /sys/kernel/debug/regmap/(something with adc in the name)/registers

18:53 <hexdump0815> xdarklight: that looks ... interesting :) - here are the adc registers: https://pastebin.com/raw/yd1StjeL

18:56 <xdarklight> hexdump0815: can you add "regmap_write(priv->regmap, 0x30, 0x3);" to the end of meson_sar_adc_probe() in drivers/iio/adc/meson_saradc.c and see if that changes anything?

19:01 <hexdump0815> xdarklight: i'll give it a try - thanks a lot

19:02 <hexdump0815> xdarklight: btw. - this is what i get if i boot v6.4.7 on the other box with rtw88: https://pastebin.com/raw/a99vNp8f

19:03 <xdarklight> hexdump0815: -110 is -ETIMEDOUT. do you have the SD104 mode enabled on the SDIO controller?

19:03 <xdarklight> *SDR104

19:04 <hexdump0815> xdarklight: it uses the default s905w settings, so maybe - which modes shall i disable maybe?

19:06 <xdarklight> hexdump0815: try the settings from meson-sm1-ac2xx.dtsi - so adding sd-uhs-sdr104; and use max-frequency = <200000000>;

19:25 <hexdump0815> xdarklight: what shall i say - with your meson_sar_adc_probe() addition the measured clock now is fine and audio playback seems to be working well :)

19:33 <hexdump0815> xdarklight: sd-uhs-sdr104; and max-frequency = <200000000>; did not change anything wrt rtw88

20:38 <xdarklight> hexdump0815: let's skip the rtw88 topic for now and focus on the GXLX clock problem. next step is to undo all previous debug changes to drivers/clk/meson and just change line 131 (which originally is: meson_parm_write(clk->map, &mpll->sdm_en, sdm > 0 ? 1 : 0);) to: meson_parm_write(clk->map, &mpll->sdm_en, 0);

20:39 <xdarklight> hexdump0815: with that change I'm interested in clk_summary and meson-clk-msr debugfs outputs from both of your boards

20:39 <xdarklight> hexdump0815: (you can keep the saradc change while testing this)

20:41 <lvrp16> I get the same problem as hexdump0815 with rtl8821cu on lwfingers branch

20:46 <xdarklight> lvrp16: someone also reported to me that rtl8821cu was not working for them on Friday but I had to refer them to the mailing list since I don't have much time and no rtw88 USB hardware. but I can't find any thread on the mailing list yet :/

20:47 <lvrp16> xdarklight: ok I will send some an email out as I found this issue yesterday. I can also ship some hardware if you would like.

20:49 <lvrp16> I recall it working before so I will also do a bisect later.

20:53 <hexdump0815> xdarklight: in which file should this change be done? - i assume clk-mpll.c but cannot find that line in there - this is v6.4.7 right now

20:55 <xdarklight> hexdump0815: ah sorry, that change should be done in clk-mpll.c

20:56 <xdarklight> hexdump0815: ah, my bad

20:56 <xdarklight> hexdump0815: https://elixir.bootlin.com/linux/latest/source/drivers/clk/meson/clk-mpll.c#L148 just change this 1 to 0

20:56 <hexdump0815> xdarklight: which line would it be in v6.4.7? - looks like it changed as there are only other lines with sdm_en in there

20:56 <hexdump0815> oh - you already wrote it - sorry

21:00 <xdarklight> lvrp16: thanks for the offer but I currently have too many online and offline projects already. if Sascha Hauer doesn't have an RTL8821CU yet then you could offer him one, he's the one who has driven the rtw88 USB code upstream

21:21 <hexdump0815> xdarklight: here are the results - audio is not smooth on both boxes now this way as measured amclk is not less off in the other direction: s905l2 https://pastebin.com/raw/2sH5XKAG - s905w https://pastebin.com/raw/jMYhWbXJ

21:22 <hexdump0815> btw. we can debug rtw88 whenever you like as i do not really need it, but debugging is ok if you are interested in it - just ping me whenever you want

21:25 <xdarklight> hexdump0815: so that bit in the SAR ADC register space at least does not control SDM (which is good, as this is a major part of MPLL clock's concept). but it means that it's totally unclear why that bit is even there in the ADC register space or what exactly it does. we'll have to ask Amlogic about this

21:27 <xdarklight> hexdump0815: I'm heading to bed now. let's continue the discussion tomorrow

21:32 <f_> lvrp16: you keep wanting to send boards :)

21:32 <f_> Thanks again BTW

21:35 <hexdump0815> xdarklight: sure - good night - there is no hurry from my side and i now even have a hack to make audio work, so we can debug this completely at your preferred pace

22:24 <lvrp16> f_: this is a wifi dongle. Rtl8821cu recently done by oengutronix

22:24 <lvrp16> Pengutronix

22:24 <f_> Ah