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02:33
<
lvrp16 >
narmstrong: I don't see any logic in firmware/scp_task/pwr_ctrl.c for vrtc wakeup on the GXL series. is it somewhere else?
02:37
<
lvrp16 >
ahh nvm, timera
02:46
<
lvrp16 >
narmstrong: so they just renamed timera to vrtc after gxl?
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narmstrong >
lvrp16: the logic hasn’t changed at all, vrtc only sets this timera value
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10:24
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f_ >
Hey all. I'm done with pctl init. Will push and test!
10:24
<
f_ >
Would be nice to have a memtest tool inside BL2, too, just in case.
10:43
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lvrp16 >
f_: yeah would be great to autotest for the eye.
10:44
<
f_ >
The real question now is, how do I achieve that?
10:45
<
f_ >
I could reuse Amlogic's port of a memtest tool for BL2, but meh. After seeing that many addresses weren't accessible I don't think it's very reliable.
10:46
<
f_ >
Their memtest tool is just a port of a public domain memtest software.
10:46
<
lvrp16 >
Not sure myself, linux-sunxi people did it before.
10:47
<
f_ >
Not sure about the fact that it's just a port?
10:48
<
lvrp16 >
I don't know how it applies to DDR4.
10:49
<
f_ >
Despite the fact that gxbb BL2 supports LPDDR2 and LPDDR3, I think most (all?) gxbb boards use DDR3
10:50
<
f_ >
well, I'm not aware of any gxbb board using LPDDR.
10:51
<
f_ >
That's mostly the main mods Amlogic made to DDR init after BL2 sources were removed from the U-Boot tree
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<
f_ >
I think the actual memtest source code is somewhere else in the U-Boot tree...such a mess.
10:59
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f_ >
>Copyright (c) 1998 by Michael Barr. This software is placed into the public domain and may be used for any purpose
11:16
<
f_ >
Now that I think about it
11:16
<
f_ >
Figuring out BL2's base address on gxbb was easy, because of old sources, but chances are it might have been changed in gxl
11:17
<
f_ >
If it changed I might possibly have a way to figure it out? Maybe?
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f_ >
Ok. For now let's start without any memtest tool.
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12:22
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f_ >
The memtest for now is.....if it can load the image then it's a success
12:23
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f_ >
Before, I was left with BL2 trying to load SCP_BL2 into memory using memcpy which crashed the board.
12:23
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f_ >
(so thought it was a memory issue)
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14:59
<
f_ >
Fails to init PLL.
15:01
<
f_ >
VERBOSE: DDR: Initialising PLL
15:01
<
f_ >
That's all it prints
15:01
<
f_ >
VERBOSE: Generic delay timer configured with mult=1 and div=24
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f_ >
Think I probably done something wrong.
16:17
<
f_ >
It can't initialise.
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f_ >
I think I skipped some stuff.
17:07
<
f_ >
Surprised pll_init in the old sources is documented
17:16
<
f_ >
The code found by Ghidra is quite straightforward though.
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f_ >
I made it just run this:
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f_ >
printf("waiting for: ");
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f_ >
udelay(10000000);
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f_ >
printf("hello\n");
18:47
<
f_ >
This is what I get:
18:48
<
f_ >
Is that a....watchdog?
18:49
<
f_ >
Or did I forget to init some stuff?
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