#linux-amlogic on 2023-06-24 — irc logs at libera.irclog.whitequark.org

2021-06-01 12:24 narmstrong changed the topic of #linux-amlogic to: Amlogic mainline kernel development discussion - our wiki http://linux-meson.com/ - ml linux-amlogic@lists.infradead.org - official channel moved from Freenode - publicly logged on https://libera.irclog.whitequark.org/linux-amlogic

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08:47 <f_> hi

08:48 <f_> back!

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10:01 <f_> Since they're writing register dumps I'll create a struct that has them all.

10:01 <f_> Did I mention that a lot of the acs structure is actually redefined later by BL2?

10:01 <f_> A lot of unused members are actually defined and used in BL2.

10:02 <f_> e.g. ddrs.t_pub_dxxcr is redefined later in ddr_pre_init

10:02 <f_> for example: https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/tree/bl2.c#n2168

10:03 <f_> or, for ddrs.ddr_timing_ind: https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/tree/bl2.c#n2070

10:03 <f_> Quite a mess if you ask me.

10:35 <f_> ddrs.t_pctl0_dfitphywrdata

10:36 <f_> Look at how long this register's name is! :P

10:37 <f_> Ok. back to work :P

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15:37 <f_> Realised a long time ago that figuring out how ddr_init_pctl would mean figuring out how ddr_pre_init works too.

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15:39 <f_> A huge mess.

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19:01 <f_> narmstrong: Looks like Amlogic does know some stuff about their PUB/PCTL

19:33 <f_> https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/commit/?id=ee93b88d7d17e5f8cc27873f7ec546e3dd92c5bc updated notes

19:33 <f_> I've proceeded to name every member in the ddrs_ structure.

19:33 <f_> Almost all of them

19:36 <f_> Man loading the BL2 disassembly takes a very long time :P

19:37 <f_> https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/tree/bl2.txt#n13154 Start of ACS data

19:37 <f_> which also happens to be where ddrs_ is

19:37 <f_> Named a whole lot of stuff

19:38 <f_> Actually named all of what Ghidra could find that was in ddrs_

19:38 <f_> https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/tree/bl2.txt#n13459 also found where the ddrt_ array was

19:38 <f_> (easy)

19:38 <f_> Didn't name anything yet.

19:39 <f_> https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/tree/bl2.txt#n13871 then we got plls_

19:39 <f_> *pll__

19:39 <f_> Very short

19:39 <f_> https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/tree/bl2.txt#n13891 then we got the ACS footer

19:39 <f_> https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/tree/bl2.txt#n13958 and the end

19:40 <f_> Also keep in mind that I'm actually doing all that reverse-engineering on an unmodified bl2.bin

19:40 <f_> I'm using this binary: https://github.com/LibreELEC/amlogic-boot-fip/blob/e96b6a694380ff07d5a9e4be644ffe254bd18512/wetek-play2/bl2.bin

19:40 <f_> This, specifically, without the proper ACS data injected into it.

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