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<luka177>
From device tree seems like Ethernet uses g12 drivers
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<f_>
Hey all. As you can see, I took a little break from Amlogic stuff. Now I'm going to resume and continue working on BL2!
<f_>
Let's do this!
<f_>
So I now know exactly what Amlogic are doing to initialise the DRAM
<f_>
What I don't know though, is how it works exactly (e.g. what is <insert DDR-related register here> register used for?)
<f_>
Amlogic only documented DMC registers, but left us with no other DDR-related registers being documented.
<f_>
But I technically can, with the reverse-engineered code I have, rewrite DDR initialisation code.
<f_>
***technically***
<f_>
But obviously I won't even be able to understand what it'll do without proper documentation/reverse-engineering of registers.
<f_>
Anyways..enough talking...let's run ghidra.
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<f_>
Also one thing to note (obviously) DDR init functions sometimes refer to stuff that is most likely supplied by acs.bin
<f_>
I'll try decompiling a BL2+ACS binary and see if that's the case.
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<f_>
I actually just saw that with a NanoPi-K2 ACS and BL2 it fails to init the DRAM and resets a couple of times before it succeeds....same behaviour as with my TF-A BL2..
<f_>
(and it eventually succeeds)
<f_>
So yeah, anyone with a NanoPi-K2?
<f_>
chewitt (logs...): Got a NanoPi-K2?
<f_>
Meanwhile I'll take a break from BL2 and concentrate on BL30.
<f_>
That does mean we'll have to (probably) maintain our own firmware.
<f_>
So..we know that Amlogic used a Cortex-M3 as the SCP on the S905.
* f_
gives up quickly and goes back to BL2.
<f_>
Going back to BL2
<f_>
If BL2+the NanoPi-K2's acs.bin results in the exact same behaviour as my BL2+the NanoPi-K2 timing.h
<f_>
Then that does mean the problem is in the timings!
<f_>
So BL2 resetting itself when trying to init the DDR multiple times is actually normal!
<f_>
It happens on Amlogic's BL2 when using the NanoPi-K2's timings, so that's normal!
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<f_>
But that does mean I have to reverse-engineer acs.bin..
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<f_>
Oh
<f_>
All that makes sense now!
<f_>
The ACS is loaded at address 0xD900A000!
<f_>
(and ends at around 0xD900A520)
<f_>
Makes sense now..
<f_>
Wait a minute...bl2.bin already has ACS data embedded...?
<f_>
Just run xxd on it and I see ACS data!
<f_>
s/run/ran/
<f_>
I guess it's a stub is it?
<f_>
I can see some changes but otherwise it's the same as the data in acs.bin!
<f_>
Who would've thought!
<f_>
And who would've thought that by reverse-engineering BL2 I can also take a look at how acs.bin is used!
<f_>
narmstrong: ^
<f_>
(previous ACS-related comments)
<f_>
If you run xxd on bl2.bin and find "acs__" you'll find the ACS footer!
<f_>
s/find/look for/
<f_>
Now DDR init makes a little more sense to me.
<f_>
Still have to find and identify the acs structure data and stuff
<f_>
Makes sense now! The offsets specified in the acs.bin footer are off by 0x200!
<f_>
I'll probably create a tool that parses the ACS from a u-boot.bin.
<f_>
That'll be useful for me at least.
<f_>
(I'll call that tool "acsbaby" because the name "baby" was in my head for a while and because gxbb)
<f_>
Might have 2 options: one that generates a timing.c and another that writes human-readable info.. narmstrong: what do you think about that?
<f_>
And that LPDDR and DDR rank switches are also specified inside acs.bin
<exkcmoeadmin[m]>
generates
<exkcmoeadmin[m]>
it is easier
<f_>
?
<exkcmoeadmin[m]>
i mean generates a timing.c a
<exkcmoeadmin[m]>
option
<f_>
Yeah, definitely!
<f_>
I'm still sceptical about this being possible though.
<exkcmoeadmin[m]>
try it
<exkcmoeadmin[m]>
btw generating a kernel driver is thing
<exkcmoeadmin[m]>
in llinux
<exkcmoeadmin[m]>
\> <f_> : (I'll call that tool "acsbaby" because the name "baby" was in my head for a while and because gxbb)
<exkcmoeadmin[m]>
assbaby
<f_>
no
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<narmstrong>
A generator tool would be great
<exkcmoeadmin[m]>
yeah
<f_>
That would solve all of our acs-related problems
<exkcmoeadmin[m]>
is mi box 3 dts in the mainline , narmstrong
<f_>
s/all/most/
<f_>
But that'll only significantly affect gxbb.
<f_>
others (gxl, ...) would need to have their BL2 decrypted somehow.
<f_>
narmstrong: Is there a known way to decrypt BL2 on gxl?
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<narmstrong>
f_: I have no idea. Perhaps dump it at runtime from an upstream bl31