12:25 <icanc[m]> i feel like this could be useful only when you want logic level translation right?

12:25 <icanc[m]> otherwise just use glasgow as a logic analyzer

13:41 <omnitechnomancer> A logic analyzer is much harder to keep up with stuff than knowing its supposed to be UART traffic

13:48 <icanc[m]> I see what you mean, i still feel like tapping into rx/tx would be enough in that case

13:49 <icanc[m]> would be cool if you can do a 2x tx uart applet

13:54 <omnitechnomancer> Yea I guess that would suffice

14:02 <icanc[m]> s/tx/rx/

14:35 <icb[m]> A purpose-built app gives you options like modifying the data, or changing parameters like baud rate, number of bits, parity, stop bits separately on both ends

14:39 <icb[m]> The logic analyzer app is pretty limited in what it can capture without buffer overruns, at least until the RAM-PAK is finished, and support for it is added

14:46 <icanc[m]> would be cool if we can turn this into a better logic analyzer, hardware wise it seems like it could be better than a dslogic basic if RAM-PAK support is there

14:48 <whitequark[cis]> i do want that to happen

14:48 <whitequark[cis]> i've mostly been limited by my health

14:58 <icanc[m]> would love to contribute tbh

14:59 <icanc[m]> oh wow, i can build my own ram-pak already?

15:06 <whitequark[cis]> i would love to accept contributions in this and other areas but code review and guidance can sometimes be more taxing than just writing the thing myself

15:06 <whitequark[cis]> the tradeoff there is obvious but it is not an easy choice for me and it's been harder later

15:12 <icanc[m]> yea i agree… not sure how i can help either 😭

15:20 <whitequark[cis]> i'll try to make my life be less fucked, ideally

15:20 <whitequark[cis]> and then it'll be less of a prolbem

15:20 <whitequark[cis]> s/prolbem/problem/

15:20 <whitequark[cis]> or it gets a lot worse and i find a replacement for myself.