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<fridtjof[m]>
having a bit of trouble using a pin set + an io buffer
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<whitequark[cis]>
fridtjof: what's the issue? I think it's a little tricky but I don't quite recall
<fridtjof[m]>
oh oops
<fridtjof[m]>
i started writing a message, accidentally sent it, didn't notice and went to get some food lol
<fridtjof[m]>
so my assumption is (and from evaluating shapes at all points that seems to be the intention) that i can treat a pin set like a signal with according width, right?
<fridtjof[m]>
My use case currently is to use a set of 4 pins to output a register/signal to for ~easy viewing with an external LA
<fridtjof[m]>
now what's weird is that with .o.eq(0b1000), pin 0 is low (correct) but 1-3 are high regardless
<whitequark[cis]>
how are you using .oe?
<fridtjof[m]>
.eq(1)
<whitequark[cis]>
try `0b1111
<whitequark[cis]>
* try `0b1111`
<whitequark[cis]>
* try 0b1111
<fridtjof[m]>
i already checked that the LA's channels are fine (swapped some) and had a friend reproduce it
<whitequark[cis]>
(if 0b1111 fixes it this is a bug in Glasgow)
<whitequark[cis]>
oh
<whitequark[cis]>
nevermind I found the bug
<fridtjof[m]>
whitequark[cis]: already tried that (to no avail), but print(oe.shape()) gave me unsigned(1) anyway so that shouldn't matter
<fridtjof[m]>
i guess i'll just cherrypick that into my branch for now so i can run tests
<fridtjof[m]>
oh wait that doesn't include get_port i guess
<whitequark[cis]>
yes
<whitequark[cis]>
there's a few pieces missing
<whitequark[cis]>
I think you can try filling them in
<fridtjof[m]>
hmm
<fridtjof[m]>
I filled in get_ports to see how far that would take me; but now amaranth's failing to elaborate a (generic) Buffer because that only accounts for SingleEndedPort and DifferentialPort and raises otherwise. I'll probably just wait this out then
<whitequark[cis]>
look at how the tests are done in QSPI controller
<whitequark[cis]>
it elaborates manually with SimulationPlatform
<whitequark[cis]>
that's the part you need
<fridtjof[m]>
ohhhh
<fridtjof[m]>
i didn't realize there was more to it
<fridtjof[m]>
oh wow i think im actually starting to get why the whole portgroup etc stuff was sorely necessary
<fridtjof[m]>
i really like how explicit the test setup is in those tests as opposed to my current "run_simulated_applet()" call