dgilmore changed the topic of #fedora-riscv to: Fedora on RISC-V https://fedoraproject.org/wiki/Architectures/RISC-V || Logs: https://libera.irclog.whitequark.org/fedora-riscv || Alt Arch discussions are welcome in #fedora-alt-arches
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<davidlt[m]> Today I will be cooking repos and final F37 images (incl. firmware), etc.
<davidlt[m]> StarFive posted crypto engine kernel patches, that's nice to see.
<davidlt[m]> Oh, I need to reconfigure Kojira to avoid dist repo being garbage collected
<davidlt[m]> Asahi Lina live stream in the background is always nice.
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<neil> davidlt[m]: that IPC Classes design looks really interesting
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<davidlt[m]> Oh, there is also something interesting mentioned on the web. JH7120.
<neil> 🤔
* neil is excited
<davidlt[m]> No details were shared on the patch :)
<neil> i just want my JH7110 to come in time for xmas
<davidlt[m]> I would prefer to see majority of patches on the mailing list before the board lands in the hands :)
<neil> okay.. fair :)
<neil> I _suppose_ a usable board is better than a brick ;)
<davidlt[m]> I am truly surprised how upstream is going on.
<davidlt[m]> A lot have been posted for a review already (minus PCIe of course).
<davidlt[m]> If they get their PCIe driver in U-Boot that will be gold.
<davidlt[m]> Another interesting thing, some cores are Sv39, some Sv48.
<neil> Yes that would be very ideal
<davidlt[m]> There is some discussions on OpenSBI mailing-list how to handle this. They wanted to change boot hart, as that defined which MMU mode is picked.
* neil finds the riscv isa manual to refresh on these terms :)
<davidlt[m]> It's how many bits are used in the address.
<davidlt[m]> 39-bit, 48-bit, 57-bit.
<neil> yeah, interesting. i've not looked at this low-level stuff since university heh
<davidlt[m]> 57-bit VA has it's own problem as I mentioned few days ago. That will break things like OpenJDK, Golang, etc.
<davidlt[m]> and QEMU will default to the max supported (which just happened to be Sv57).
<neil> right... so basically fun* upstream work to try and get them compatible with 57-bit VA?
<davidlt[m]> RISC-V doesn't have internal bits wired like arm64 or x86_64 where mmap + hints allow userspace to request memory from new higher space.
<palmer> we should probably add them, though
<davidlt[m]> I also a bit excited about Zbb optimized string functions in the kernel :)
<davidlt[m]> I wonder if that could be applied to JH7110.
<davidlt[m]> palmer: from what I understand this is how arm64 and x86_64 works (didn't look at the code, just documentation and LWN articles).
<palmer> ya, that's all I did too
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<palmer> do you have a jh7110 yet? I've gotten some Kickstarter messages, but no HW
<davidlt[m]> I also quickly looked at Golang and something else. It's all random guesses (let's call it magic) to calculate the hint properly.
<neil> palmer: same position here. messages but no HW as of yet
<davidlt[m]> palmer: yes, I got dev sample from PINE64, but didn't play too much (it comes with no software).
<davidlt[m]> So it's a bit expensive time wise to do a lot of guess work.
<davidlt[m]> Icenowy has a tree, but didn't want (couldn't?) share a disk image to play around.
<davidlt[m]> It's being produced for some time now. I think there should be an update on KS with some pictures.
* davidlt[m] checks...
<davidlt[m]> I am not sure if you get it before Christmas madness happens with shipping.
<davidlt[m]> The final Fedora/RISC-V 37 cooked (hopefully)! Time to download and start cooking other bits.
* kalev is waiting for the new VisionFive 2 board to arrive to play with this.
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