dgilmore changed the topic of #fedora-riscv to: Fedora on RISC-V https://fedoraproject.org/wiki/Architectures/RISC-V || Logs: https://libera.irclog.whitequark.org/fedora-riscv || Alt Arch discussions are welcome in #fedora-alt-arches
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<davidlt[m]> Meteor Lake might have L4 cache.
<davidlt[m]> I hope it gets Thunderbolt 5 too. This would be an interesting little thing from Intel.
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<davidlt[m]> Wow
<davidlt[m]> Now we just need NBD client support in U-Boot :)
<davidlt[m]> I wonder if this will finally allow running on cores with different ISA on x86: https://www.phoronix.com/news/Intel-IPC-Classes-Post-RFC
<davidlt[m]> I always considered Intel Thread Director just a step towards that. We already had SoCs that have different ISA in the cores, even Alder Lake P/E cores are different (AVX512 exist in P cores).
<davidlt[m]> It's kinda a Holy Grail if you manage to schedule/balance across those cores.
<davidlt[m]> Like most cores don't need AVX512 in them.
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