<davidlt[m]>
Proof that I am not awake yet. Going to YouTube to search for Python3.12 package (instead of looking at dist-git).
<davidlt[m]>
It seems that RX 6600, 6650, or even 6750 could become a good replacement for RX 570, 580 cards once it gets to ~200 USD or below.
<davidlt[m]>
Finally something that could replace Polaris, but sadly RNDA/RNDA2 will not work on riscv64 IIRC.
<davidlt[m]>
Rust 1.64.0 just landed. Time to look at 1.65.X and later test 1.66 beta and report if that works.
<davidlt[m]>
kernel 6.0.10 is also almost done (RPMs being written out now).
<davidlt[m]>
Coffee is here, just need to find a nice playlist to begin properly looking into things.
jcajka has joined #fedora-riscv
<davidlt[m]>
I am actually doing 3 Rust 1.65.0 builds to speed up things.
<davidlt[m]>
A few possible variations of what I expect to happen.
davidlt has quit [Ping timeout: 260 seconds]
davidlt has joined #fedora-riscv
<davidlt[m]>
So it looks like that 1.65.0 with patched 1.64.0 is compiling so far (which is a bit annoying).
<davidlt[m]>
I wonder if I will be able to compile 1.66.0 with unpatched 1.65.0, or not.
<davidlt[m]>
This definitely will be quite annoying.
<davidlt[m]>
Ah, btw, since QEMU got support for Sv57 (5-page table) that breaks a bunch of stuff (OpenJDK, Golang, etc.).
<davidlt[m]>
There is a patch to add something like: -cpu rv64,satp-mode=sv48
<davidlt[m]>
Instead of QEMU going for the latest highest mode.
<davidlt[m]>
In general Sv39 and Sv48 should be safe options. There are discussions how to support anything beyond that. x86_64 and aarch64 by default don't allocate anything high, and it relies on mmap hints to ask for it.
<davidlt[m]>
So if you have some interesting crashes be aware.
<davidlt[m]>
Does not apply to physical machines are all of them only support Sv39.
<davidlt[m]>
So this kernel patch "[PATCH v8 0/3] riscv, mm: detect svnapot cpu support at runtime" is for "marking contiguous 4K pages as a non-4K page". That is support for pages beyond 4K. Probably will be required for RVA23.
<davidlt[m]>
IIRC only 64K is allowed right now thus something like 16K (like on Apple M1/M2) wouldn't be valid.
<davidlt[m]>
There is also (today): RISC-V V C Intrinsic API v1.0 release meeting reminder (November 28th, 2022)
<dgilmore>
davidlt[m]: I am using a radeon 6500 XT in my ampere workstation. sadly its still very rough. needed some code isolated and compiled with floating point support