02:04 <_whitenotifier-4> [amaranth-boards] whitequark reviewed pull request #254 commit - https://github.com/amaranth-lang/amaranth-boards/pull/254#discussion_r1958962348

13:06 <Stas[m]1> Speaking on the serdes in ECP5 - does only the "5G" version of FPGA have them?

13:09 <whitequark[cis]> non-5G ECP5 devices have a 3 Gbps capable SERDES

13:12 <lf[m]> LEF5UM has serde and the LEF5U not. Or can one enable serde on u variant?

13:13 <whitequark[cis]> oh, yeah, not all of them have serdes

13:13 <whitequark[cis]> lattice has a table explaining this

13:14 <Stas[m]1> Thanks for the clarification! I will check if my board has them, as serdes is interesting for HDMI output

13:14 <Stas[m]1> Probably will not have enough channels, as HDMI needs 4

13:15 <vup> depending on resolution / framerate, you can get by with just the normal IOs for HDMI

13:15 <whitequark[cis]> in fact I would generally do that, since it's a fair bit easier to get running

13:22 <Stas[m]1> This is what I am about to try for my PC Engine interface. I wired it out to use LVDS pins, and that should give me 640x480

13:23 <Stas[m]1> For now I am just messing with VGA out, as it removes a whole layer of issues while developing

13:23 <Stas[m]1> R2R DAC is king :D

13:23 <lf[m]> Is there a resource to learn about DDR gearing and ddrdll? I want to interface with an SD card interface.

13:31 <vup> Stas[m]1: you should be able to get much more, 1080p30 atleast, without event exceeding the specified IO timings. In my experience you can even go higher usually.

13:36 <vup> lf[m]: I have never done a SD card interface specifically, what kind of resources are you looking for? I mainly looked at FPGA-TN-02035 (ECP5 and ECP5-5G High-Speed I/O Interface) to figure out the specifics for ECP5 FPGAs in the past.

13:40 <lf[m]> Was hopping for a blog article that gives an overview on what the common mistakes are so I don't need to find that out myself. But I think I need to find out how to do bidir DDR and how to do 90° phase shift for sample clock

13:43 <Stas[m]1> <vup> "Stas: you should be able to..." <- Wow! Now I am more hopeful. Just checked and my FPGA lacks a serdes, so will try how far I can get.

14:37 <_whitenotifier-4> [amaranth-boards] eibach reviewed pull request #254 commit - https://github.com/amaranth-lang/amaranth-boards/pull/254#discussion_r1959883559