<zyp[m]>
doesn't litex leave the interrupt implementation entirely up to the glue code, since it's common to deviate from the standard?
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<jfng[m]>
the old scheme with custom CSRs wasn't spec compliant, whereas the current one is compatible with a PLIC while still allowing for up to 16 interrupt lines to be controlled by the cpu
<jfng[m]>
iirc i got the idea from the ariane core, which is also in litex
<cr1901>
jfng[m]: Yea, and generally I agree with your strategy (and also, Minerva is quite pleasant to read, be proud :D). Unfortunately, one thing I wanted from Sentinel was turnkey Rust experience, and the riscv-runtime punts the high 16 interrupt bits to supporting crates
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<cr1901>
if I leave the top 16 bits undefined, users won't have to bring in any special code to do interrupts; "just" OR everything with machine external
<_whitenotifier-4>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 7353d66 - Deploying to main from @ amaranth-lang/amaranth@54dd41da3a8b5908cf16acd82ce0ece0c58de77e 🚀
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