whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · play https://amaranth-lang.org/play/ · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<pepijndevos[m]> I see there is an amaranth-soc repo that is kinda undocumented. Are there any soc examples or anything like that?
<pepijndevos[m]> I want to do something kinda like https://github.com/olofk/corescore/blob/master/sw/corescorecore_gen.py except without the ugly generating verilog step. Just instantiate a dozen mostly independent riscv cores and then make them talk to each other
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<whitequark[cis]> <pepijndevos[m]> "I see there is an amaranth-soc..." <- I think jfng had one
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<jfng[m]> but it may not be up to date
<jfng[m]> i'm a bit sick today, but i'll try to update in a day or so
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<jorolf[m]> Maybe there is an easy way to replace parts of the design based on whether it's being simulated or synthesized?
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<zyp[m]> the platform argument will be None when elaborated for simulation
<zyp[m]> and with the right persuasion, you can probably get the simulator to simulate them too; I've done it before
<zyp[m]> but that was before the last simulator changes and SimulationPort and friends, so my old code is defunct and I haven't looked into how to update it yet
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<zyp[m]> the key is that by using the changed-trigger on the clock signal, rather than the tick-trigger on the clock domain, you can act on both edges
<whitequark[cis]> Glasgow has some code simulating DDR buffers I think
<whitequark[cis]> I'll dig it out once I have a keyboard
<zyp[m]> how was it, the main reason we don't have first class support for DDR buffers yet are because timings are platform specific, so there's no single generic model?
<whitequark[cis]> i think it was just about the difficulty of attaching processes to elaboratables
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<RobTaylor[m]> <pepijndevos[m]> "I see there is an amaranth-soc..." <- wip documentation here https://github.com/amaranth-lang/amaranth-soc/pull/82
<RobTaylor[m]> RobTaylor[m]: you can take a look at https://github.com/ChipFlow/imec-workshop/tree/reference
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<pepijndevos[m]> <RobTaylor[m]> "you can take a look at https://..." <- omg a wild chipflow appears haha oh right your entire thing is making amaranth socs super easy hmmmmm
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<RobTaylor[m]> <pepijndevos[m]> "omg a wild chipflow appears haha..." <- ?