00:10 <ddribin[m]> Does plat.default_rst override that power-on-reset ready signal? Or augment it?

00:12 <ddribin[m]> Oh, I see. `default_rst` must be `None`:... (full message at <https://catircservices.org/_irc/v1/media/download/AUEYDNHKsWo28zcDV33hKpvwcGWm1W91QW8fnj4N1rehzcotyLTwrLpQfF1MGTwHXoLXcjrJJV5AA7qMhR5hvXq_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9UQ1lCc3pUS3BLSU5jemdIRlVLZGRac1A>)

00:25 <ddribin[m]> Setting `platform.default_rst = "button` does work, though it does not get run through a `FFSynchronizer`... probably doesn't matter

00:29 <ddribin[m]> can't quite figure out how to setup a new clock domain 🙂 I don't think I have access to the clock signal? anyhow, I have something working. thanks!

00:29 <cr1901> The reset signal itself should get run through an ResetSynchronizer (mildly different from FFSynchronizer)

00:35 <ddribin[m]> Ah, yup, it does

00:46 <cr1901> The default reset logic isn't that much to copy; when I did the "platform.default_rst = "button"" trick, it's because this is an example design and I didn't want to spend time interfacing the default logic into my source for a single change from default

00:51 <ddribin[m]> what is the drawback to using default_rst ? Seems like the intent of Platform.dfault_rst is to setup a reset button?

00:53 <cr1901> Some boards (Arty A7) have a button that is explicitly dedicated to being a design reset (I think this means it uses global routing; I would have to check Arty A7 docs)

00:54 <ddribin[m]> okay. I'll fiddle around with a new clock domain a bit later, to see if I can get that working

00:55 <cr1901> https://github.com/amaranth-lang/amaranth-boards/blob/main/amaranth_boards/arty_a7.py#L17-L21

00:56 <cr1901> icebreaker has no such button, so... I lie and say one of the user buttons is a reset button :P https://github.com/amaranth-lang/amaranth-boards/blob/main/amaranth_boards/icebreaker.py#L25

00:57 <ddribin[m]> I mean, that seems reasonable, right 🙂 we're declaring that this button *is* the reset button

00:59 <cr1901> Sure, but I explained to you what I was doing; since I'm deviating from the built-in reset logic, even just a little, it's probably less surprising to ppl who don't know Amaranth to see explicit reset logic to indicate "hey, I'm doing something not default"

01:01 <duskwuff[m]> in some cases it just means the button is literally labeled "RESET"

01:02 <cr1901> In short, I got lazy, and didn't feel like copying; ice40 is a bit special since the default reset logic works around a hardware bug. Maybe a future RFC could expose the platform-specific resets to user code for small changes where the user doesn't need that much custom logic, Idk...

01:05 <whitequark[cis]1> I think you can just copy paste it

01:06 <cr1901> Perfect is the enemy of finished; I'll come back to it after I finish Sentinel's docs and take a break (8 last items to document)

01:09 <ddribin[m]> I'm not even sure what I should copy and paste. This won't work since there is no `clk_i` signal:... (full message at <https://catircservices.org/_irc/v1/media/download/AWH77SyQzPEyWFakK5wWqbYhs8R7KKBBH_k32VF-KWLmAd601rSccmd0C_eE76uiitmBy3XXmNzSHr9QojJMQ6e_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9tY3hSSWJMR2lMU0JMekJsbFRmS2tmbUo>)

01:10 <cr1901> m.d.comb += ClockSignal("sync").eq(platforn.request(platform.default_clk).i)

01:10 <cr1901> minus typos

01:18 <ddribin[m]> Okay, so this works:... (full message at <https://catircservices.org/_irc/v1/media/download/AavYsPMWxj-CNxF-vscXZDWGm1QRZW_9a9MetkrcVeUaKKnah_cpNsL5qtxEhuITJci2NxI7scJhXcohGWNJUUu_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9BS3B1bHRRa1ZTVERtWEJnU1lxemVhREc>)

01:21 <ddribin[m]> but I believe this also overrides the 3us power-on-reset delay described here (unless I copy all of that, too):... (full message at <https://catircservices.org/_irc/v1/media/download/AeRj0SVDXPcHV3Dx6jwYdCLnhrP04FpB7bvfPgPVnicdKeKXBXKFXlgBPHn7e-SroDFeumdR0joZXum_gdLNHf-_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9QYWNEWElQRE55UWVMdlhvdFR4aUNRQmE>)

01:22 <cr1901> Correct, that logic won't be brought in, which is the point I got lazy and used my hack :P

01:28 <cr1901> _IIUC_ (please wait for others to verify/correct me), SiliconBluePlatform.create_missing_domain will not get called at all if you define "m.domains += ClockDomain("sync")", as you do in your snippet: https://github.com/amaranth-lang/amaranth/blob/main/amaranth/hdl/_ir.py#L149-L152

01:29 <cr1901> collector.defined_domains will contain "sync", and therefore the missing_domain function- i.e. SiliconBluePlatform.create_missing_domain- won't be called for "sync"

01:33 <whitequark[cis]1> yes

01:33 <whitequark[cis]1> this is regretfully undocumented