<tpw_rules>
if i assert r_en on an AsyncFIFO, then i get r_data populated the next cycle. but what about the subsequent cycles if r_en is only asserted for one? in simulation the value doesn't seem to stay which is strange to me
<crzwdjk>
It kind of makes sense if you think of it as some machinery around a dual-port memory, which is what it ultimately it. r_en connects to the enable on the read port of that memory.
<crzwdjk>
tpw_rules: I think if you use AsyncFIFOBuffered it will behave like what you are expecting
<tpw_rules>
i mean that's how dual port memories work, at least the ones in intel FPGAs
<tpw_rules>
is that not always how the memories work?
<whitequark[cis]>
<tpw_rules> "if i assert r_en on an AsyncFIFO..." <- all of our FIFOs are first word fallthrough
<tpw_rules>
i wasn't sure how first word fallthrough meshed with getting the data after r_en
<tpw_rules>
doesn't fwft imply r_en is really r_ack?
<iposthuman[m]>
Curious, what does "first word fallthrough" mean?....I'm new to learning Amaranth.
<tpw_rules>
maybe i'm misunderstanding that too
<tpw_rules>
i remember when support for non-fwft was removed but never quite got why
<tpw_rules>
whitequark[cis]: based on my research the fact that the fifos are FWFT directly contradicts the description of the r_en attribute
<tpw_rules>
so i think there's either a docs bug or a code bug
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<tpw_rules>
okay, i take back my assertion that the documentation is wrong
<tpw_rules>
there is a reading that correctly explains its current behavior
<tpw_rules>
but i think it's quite ambiguous if you don't have a deep understanding of what an FWFT fifo is and how it compares to a (what other sources call) standard fifo. for example crzwdj describes non-fwft behavior above
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<Wanda[cis]>
yeah, the documentation... could be improved
<Wanda[cis]>
I didn't really know what to do with it the last time I touched it
<tpw_rules>
this is partially orthogonal, but is there a way to put timing diagrams into it?
<tpw_rules>
for r_en, could it be renamed r_ack or would that break too much?
<Wanda[cis]>
doing an alias is easy
<Wanda[cis]>
but also
<Wanda[cis]>
the plan for 0.5, I believe, is to make FIFOs use stream interface
<Wanda[cis]>
well, use whatever abstraction amaranth comes up with for stream interface; the signals are already there
<tpw_rules>
i see
<tpw_rules>
i assume they would still be easy to use manually, as it were
<Wanda[cis]>
it's literally the same thing, just repacked to use a new interface
<Wanda[cis]>
not unlike the lib.wiring migration
<tpw_rules>
ok
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<omnitechnomancer>
first word fall through means the current head is always available on the r_data if r_valid is high and r_en cycles to the next word?