05:30 <tpw_rules> if i'm doing i2s data reception, do i really need to FFSynchronize my input pin? i would have a fifo with CDC to get the samples up to a processing clock domain but could/should the serial->parallel conversion be at the i2s frequency without any synchronization?

08:16 <whitequark[cis]> <tpw_rules> "if i'm doing i2s data reception,..." <- I generally avoid multiple clock domain applets with external due to (still! they were a motivation for Amaranth itself) unresolved async reset issues

08:16 <whitequark[cis]> so you would be sampling at core frequency. 48M is usually enough

16:44 <tpw_rules> whitequark[cis]: to be clear this is not relevant to the glasgow at all

16:45 <tpw_rules> i'm just concerned that making the frequency that high relative to my ~3MHz data clock introduces lots of questions about the sampling timing

18:09 <galibert[m]> I thought having the frequency high was how you avoided the questions