<crzwdjk>
I recently rewrote my arbiter component to take advantage of lib.wiring, and it got a whole lot shorter plus more general. And it Just Works straight out of the box. Thanks, whitequark and everyone who participated in the RFC process.
<whitequark[cis]>
nice!!!
<crzwdjk>
It all works out very nicely, just a couple of python for loops to generate the needed Amaranth bits, and connect() does the heavy lifting of connecting up everything as needed without lots of tedious typing.
<crzwdjk>
Also interestingly it was one area where the old version of my code had a homebuilt proto-interfaces system of sorts.
<Darius>
crzwdjk: I love it when rewriting things makes them smaller
<Darius>
very freshly shaved face mem
<Darius>
e
<cr1901>
Wanda[cis]: Was on vacation today and just came back. Fixing the patch is waiting until at least tomorrow.
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<crzwdjk>
It also helps that I have a better idea of how to write HDL now, when I started I pretty much didn't have any idea at all. Just did the amaranth exercises by Robert Baruch and off I went. Kind of impressed my thing worked at all.
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<iposthuman[m]>
LOL, that me now. I just finished Robert's tutorials and bl0x's femto port.
<crzwdjk>
iposthuman[m]: if you have any questions, I can try to answer them from the perspective of someone who was where you are not too long ago
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<nates93[m]>
Just confirming, there's no way to simulate amaranth with verilog without converting amaranth into verilog, right?
<galibert[m]>
I don't understand the question
<galibert[m]>
You mean simulating a system that has parts in amaranth and parts in verilog?
<Wanda[cis]>
cxxrtl would be able to do it
<galibert[m]>
using yosys to do the link?
<Wanda[cis]>
mhm
<galibert[m]>
intriguing idea
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<iposthuman[m]>
That would be great and much appreciated 🙏
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<Chips4MakersakaS>
I will not be available for the SOC meeting over ten minutes
<whitequark[cis]>
me too (on vacation)
<tpw_rules>
hi, i did want to talk a bit as a prospective user
<galibert[m]>
tpw_rules: is good stuff, needs more stuff :-)
<tpw_rules>
how do i start with it?
<tpw_rules>
is there an AXI bridge anywhere that's not by That Guy?
<galibert[m]>
no, it only does wishbone
<galibert[m]>
(hence needs more stuff)
<tpw_rules>
i just want CSR magic i don't have to think about, really
<tpw_rules>
so performance isn't a concern and i can probably bash one together that works okay
<tpw_rules>
but i really don't see an entry point
<galibert[m]>
it's a collection of devices, not a framework
<galibert[m]>
the wishbone stuff is in wishbone
<tpw_rules>
how should i start using it?
<whitequark[cis]>
yeah, we would have an amaranth_soc.axi4 module for AXI stuff
<whitequark[cis]>
but ... AXI is a collection of four streams
<whitequark[cis]>
we probably want streams first
<whitequark[cis]>
*five
<galibert[m]>
is axi3 (the one I need actually) fundamentally different?
<whitequark[cis]>
not really no
<whitequark[cis]>
slightly
<tpw_rules>
like i said i'm really just here for CSR
<tpw_rules>
i picked axi4 cause i had the option and the bigger number seemed cooler
<tpw_rules>
whitequark[cis]: don't you have vacation :3
<galibert[m]>
do you have the option of picking wishbone?
<tpw_rules>
i have to convert to AXI at some point to talk to the HPS
<galibert[m]>
cyclone v?
<tpw_rules>
yeah
<galibert[m]>
it's axi3, not 4
<galibert[m]>
and optionally avalon in some places, but whatever
<tpw_rules>
hm, qsys let me pick 4. maybe it's adapting
<tpw_rules>
in any case neither of those are wishbone
<galibert[m]>
indeed
<galibert[m]>
looks like the hps-fpga bridges are axi3, and the fpga-sdram bridge is configurable axi3, axi4 and avalon-mm
<galibert[m]>
according to cv_5v4.pdf
<tpw_rules>
i'm just planning to use the fpga2hps (into the ACP) and the hps-fpga lightweight whatever
<tpw_rules>
anyway, how 2 csr
<tpw_rules>
ah, yes it does say axi3
<tpw_rules>
i'm not sure i have enough skill to tell the difference
<galibert[m]>
what's missing, wq says, is streams, because they better map to axi
<galibert[m]>
(I wouldn't know :-) )
<jfng[m]>
sorry for being late! the SoC meeting is, right now i guess
<galibert[m]>
jfng: I guess the current discussion was "gimme axi kthnx"
<jfng[m]>
_whitenotifier-f: and as you may have seen, we have a new component metadata RFC! \o/
<tpw_rules>
also docs, if we're being demanding
<jfng[m]>
AXI is very much on our roadmap, iirc somewhere in 2024 for me, unless someone wants to work on it before
<jfng[m]>
and i am personally eager to having an alternative to WB in amaranth-soc
<tpw_rules>
i might be able to contribute a minimal AXI to CSR bridge
<tpw_rules>
but like i said earlier, i think i need some help starting to use amaranth-soc. i don't see any pointers to docs or examples at all
<tpw_rules>
(and i'm not sure if you want innocent users yet)
<jfng[m]>
amaranth-soc doesn't have documentation yet, it is also still very barebones and undergoing vast changes
<tpw_rules>
i think i have relatively simple needs
<jfng[m]>
we do use docstrings a lot, which is a start
<jfng[m]>
but some parts of amaranth-soc, such as `MemoryMap` and its address translation scheme is currently hard to understand with docstrings alone, and could really benefit from some sort of manual (and also being rewritten)
<jfng[m]>
tpw_rules: what are your needs ?
<tpw_rules>
i just want a basic CSR infrastructure, which bridges to AXI
<tpw_rules>
i can add the second part
<jfng[m]>
yeah, you will need to make your own AXI-to-CSR bridge
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<tpw_rules>
but i'm still not sure how to use the CSR components?
<tpw_rules>
does anyone have a demo design? are they stable enough for a bit? should i wait for the lib-wiring branch merge?