<tpw_rules>
i guess it's possible the pre-first-reset state of every signal could be zero
<tpw_rules>
but based on how FPGAs work that seems unlikely
<mcc111[m]>
Because when I first started using amaranth I found a bug where the construct if (false) { x() } else { y () } was never calling y() due to a bug in yosys
<mcc111[m]>
which is making me think I may be doing weirder things in the name of code generation than other users
<tpw_rules>
then i don't think you could do anything but test
<tpw_rules>
the possibility i describe would be a quirk of amaranth though
<Wanda[cis]>
I cannot exactly guarantee you won't run into any more insane bugs, but... well, they would be considered as bugs
<tpw_rules>
just to be sure, it will be optimized away even if reset is never asserted in that domain?
<tpw_rules>
like it'll be baked as 1 into the FPGA's startup configuration. i forget the verilog syntax for that
<Wanda[cis]>
so there's a few things here
<Wanda[cis]>
first, if the signal is truly never assigned, it doesn't have a domain, and just becomes a const driver of its reset value
<Wanda[cis]>
second, "reset value" in amaranth isn't literally "the value it gets on reset", it's more involved
<tpw_rules>
i knew that second thing, to some degree
<Wanda[cis]>
for combinatorial signals, "reset" is actually "the value this signal will get if not overriden by any active assignment", ie. more of a default value
<tpw_rules>
yes
<Wanda[cis]>
and for sync signals, it's both reset and initial value
<tpw_rules>
good to confirm
<Wanda[cis]>
tpw_rules: oh, it'll be baked much harder than that, in all likelihood
<Wanda[cis]>
as in, const-folded into whatever logic uses it
<tpw_rules>
yes
<tpw_rules>
but that does answer the "initial value" question, that was the thing i was (mildly) concerned about
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<ravenslofty[m]>
Well, I went ahead and flipped the switch: ABC9 is now the default for synth_ice40 and synth_ecp5.
<galibert[m]>
And now, the end of the world
<nelgau>
hooray
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<RobTaylor[m]>
<galibert[m]> "And now, the end of the world" <- at last! =)
<crzwdjk>
Should I have been using ABC9 all along? How does one do that from amaranth?
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<jfng[m]>
hi! it is time for the weekly SoC meeting
<jfng[m]>
still no RFC on the agenda, the work on component metadata for the peripheral API has seen good progress (i now have a prototype that can generate a JSON description of a simple SoC), but its RFC is still WIP
<jfng[m]>
since we have cancelled a few meetings recently, i thought about using this one to answer any questions from anyone who has been using amaranth-soc recently
<jfng[m]>
e.g. @galibert:matrix.org , @libera_cr1901:catircservices.org
<galibert[m]>
Didn't touch amaranth recently, been doing other things (like Cyclone V RE)
<galibert[m]>
Just wondering though, what's the status w.r.t interfaces as this point?
<jfng[m]>
wishbone and CSR bus interfaces have been migrated to lib.wiring, and every bus primitive has been converted to components
<galibert[m]>
Beautiful
<jfng[m]>
this should incur some minor breakage in existing designs, but changes are hopefully one-liners
<cr1901_>
jfng[m]: I'm sorry, I was afk during the meeting. You have been helpful answering my questions when they came up. I still think sparse addr translation for more granularity/width combos would be valuable to me, but I need to think about that more
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<iposthuman[m]>
Hi, I'm relatively new to Amaranth and was wondering where the link is for the SoC you talking about? 🙂
<galibert[m]>
amaranth-soc on github next to amaranth-lang
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