whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<iposthuman[m]> I been reviewing Amaranth's examples and I'm not sure what *por.py* and *sel.py" and doing. What is "por" and what does ```ClockSignal().eq(cd_por.clk)``` do if the circuit isn't assigned to anything?
<whitequark[cis]> power-on reset
<iposthuman[m]> Ah. thanks.
<iposthuman[m]> Also, what is the sel.py example trying to demonstrate?
<whitequark[cis]> word_select being usable on lhs and rhs
<iposthuman[m]> Ok. thanks.
<iposthuman[m]> I had asked last week about one-hot usage and mentioned I thought the Decoder would be useful but the responses I got didn't really answer my question. So I saw the *pmux.py" example and it "seems" like it could be taken as generting one-hot decoding using switch statement, for example, ``` with m.Switch... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/aUFKpBSDnkBiSsLdvfCTiGbq>)
<iposthuman[m]> I'm making an incorrect assumption?
<whitequark[cis]> no, you got it right
<iposthuman[m]> Oh, Nice! sweet.
<iposthuman[m]> Funny thing is I created what I thought would be interpreted as generating one-hot but is actually increased the LUT count by 50+ : ```... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/drycusUZZzuBcHOqldvLUEUi>)
<iposthuman[m]> Less LUTs where used using this style: ``` with m.Switch(funct3) as alu:... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/vaZrKnDvCQmEyKSyXnuhRohE>)
<iposthuman[m]> But now that I know of the "---1-" syntax I will try that 😉
<iposthuman[m]> Thanks Catherine
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<galibert[m]> iposthuman: last week I told you going through explicit one-hot will not make things better and possibly make them worse. Looks like I was right
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<_whitenotifier-b> [amaranth] whitequark opened pull request #955: back.verilog: require Yosys >=0.35 - https://github.com/amaranth-lang/amaranth/pull/955
<_whitenotifier-b> [amaranth] whitequark edited pull request #955: back.verilog: require Yosys >=0.35 - https://github.com/amaranth-lang/amaranth/pull/955
<_whitenotifier-b> [amaranth] whitequark closed issue #934: Allow `isinstance()`/`issubclass()` to work between Interface and FlippedInterface - https://github.com/amaranth-lang/amaranth/issues/934
<_whitenotifier-b> [amaranth] whitequark commented on issue #934: Allow `isinstance()`/`issubclass()` to work between Interface and FlippedInterface - https://github.com/amaranth-lang/amaranth/issues/934#issuecomment-1821063928
<_whitenotifier-b> [amaranth] codecov[bot] commented on pull request #955: back.verilog: require Yosys >=0.35 - https://github.com/amaranth-lang/amaranth/pull/955#issuecomment-1821066010
<_whitenotifier-b> [amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-955-f9da3c0d166dd2be189945dca5a94e781e74afeb - https://github.com/amaranth-lang/amaranth
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<_whitenotifier-b> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 1 commit to main [+0/-0/±2] https://github.com/amaranth-lang/amaranth/compare/f9da3c0d166d...fc06dd7644f9
<_whitenotifier-b> [amaranth-lang/amaranth] whitequark fc06dd7 - back.verilog: require Yosys >=0.35.
<_whitenotifier-b> [amaranth] whitequark closed issue #931: Amaranth emitted invalid Verilog (Amaranth conditionals containing only comb assignments results in Verilog "empty case" error) - https://github.com/amaranth-lang/amaranth/issues/931
<_whitenotifier-b> [amaranth] whitequark closed pull request #955: back.verilog: require Yosys >=0.35 - https://github.com/amaranth-lang/amaranth/pull/955
<_whitenotifier-b> [amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-955-f9da3c0d166dd2be189945dca5a94e781e74afeb - https://github.com/amaranth-lang/amaranth
<_whitenotifier-b> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+0/-0/±32] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/58cebf75ab37...cd6564441f26
<_whitenotifier-b> [amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] cd65644 - Deploying to main from @ amaranth-lang/amaranth@fc06dd7644f9da7379a51c62b7c7fd0cdbd2a97f 🚀
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<_whitenotifier-b> [amaranth] wanda-phi opened pull request #956: lib.wiring: fix search-and-replace accident. NFC - https://github.com/amaranth-lang/amaranth/pull/956
<_whitenotifier-b> [amaranth] codecov[bot] commented on pull request #956: lib.wiring: fix search-and-replace accident. NFC - https://github.com/amaranth-lang/amaranth/pull/956#issuecomment-1821231240
<_whitenotifier-b> [amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-956-fc06dd7644f9da7379a51c62b7c7fd0cdbd2a97f - https://github.com/amaranth-lang/amaranth
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<_whitenotifier-b> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth/compare/fc06dd7644f9...1802f7fddd95
<_whitenotifier-b> [amaranth-lang/amaranth] wanda-phi 1802f7f - lib.wiring: fix search-and-replace accident. NFC
<_whitenotifier-b> [amaranth] whitequark closed pull request #956: lib.wiring: fix search-and-replace accident. NFC - https://github.com/amaranth-lang/amaranth/pull/956
<_whitenotifier-b> [amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-956-fc06dd7644f9da7379a51c62b7c7fd0cdbd2a97f - https://github.com/amaranth-lang/amaranth
<_whitenotifier-b> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+0/-0/±32] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/cd6564441f26...e0ccace78cdf
<_whitenotifier-b> [amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] e0ccace - Deploying to main from @ amaranth-lang/amaranth@1802f7fddd95112ce0d9e2d7018359dcc9cf5bc6 🚀
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<_whitenotifier-b> [amaranth] cr1901 reviewed pull request #954 commit - https://github.com/amaranth-lang/amaranth/pull/954#discussion_r1400978829
<cr1901> Wanda[cis]: Re the flake8 comment: the "parens is preferred to line-continuation" is a new one for me. I try to make sure my code passes PEP8 (in bursts). But since flake8 doesn't complain about this, I didn't know about it until today
<cr1901> That means... well, lots of code of mine needs to corrected (probably not happening), but I can at least add something to make it so I don't run afoul of the rules in _other_ ppl's projects
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<Wanda[cis]> I mean, that was a nit-level comment...
<Wanda[cis]> but also, uh, please fix the parentheses grouping actually
<cr1901> Oh. Uhhh... the PR doesn't work anymore. That's not good
<Wanda[cis]> yup.
<cr1901> I should probably fix that
<Wanda[cis]> I just said that, yes
<cr1901> I mean, we could ship it and hope nobody notices, but I don't think that's fair :P
<cr1901> (I didn't run the tests obviously. I didn't think I could f*** up two parens.)
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<cr1901> Okay, looks like everything's passing now
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<ralph93> wonder if they've heard of amaranth https://philippos.info/hipernetch/Simulation_RTL_and_Generator/
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<vipqualitypost[m> hmm... my amaranth install somehow broke, so i reinstalled it following instructions from the docs: I can import amaranth in the REPL but when I try to do so from an actual script it can't find the module
<vipqualitypost[m> pip list does show it, also.
<iposthuman[m]> Does anyone have an example of using SRAM? I have setup a board definition using: ``` SRAMResource(0, # Default name = "sram"... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/WRIlADpbLPBYUqrYISIYbYBA>)
<iposthuman[m]> I'm trying to figure out how to use the *dm_n* bank fields. This is what I try but it fails: ``` sram_0 = platform.request('sram', 0)
<iposthuman[m]> sram_0_lb = sram_0.dm(0)
<iposthuman[m]> ```
<iposthuman[m]> What is *dm_n* being built as? I also tried ```sram_0_lb = sram_0.dm.lb``` but it doesn't know of *lb*
<adamgreig[m]> sram_0.dm_n.o and .oe?
<adamgreig[m]> I'm not sure if _n implicitly makes it inverted and removes the _n, I always write that explicitly
<adamgreig[m]> * sram_0.dm_n.o?
<iposthuman[m]> It can see dm but not sure how to access what comes after
<iposthuman[m]> I can access the *cs, a, oe* but can't figure out *dm* because it is actually two pins
<iposthuman[m]> *memory.py* is configuring as: ``` if dm_n is not None:
<iposthuman[m]> io.append(Subsignal("dm", PinsN(dm_n, dir="o", conn=conn))) # dm="LB# UB#"
<iposthuman[m]> ```
<iposthuman[m]> i even tried ```sram_0_lb = sram_0.dm(0)```
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<adamgreig[m]> Probably .dm.o[0] and [1]
<iposthuman[m]> ok. i tried ```sram_0_lb = sram_0.dm[0]``` and that compiled. not sure i'm getting what i expect.
<adamgreig[m]> You're still missing .o
<iposthuman[m]> that works but the signal is an *input* not an output ```sram_0_lb = sram_0.dm.o[0]```
<iposthuman[m]> so that confused me
<galibert[m]> .i then
<adamgreig[m]> Aah, sorry! Yea .i
<adamgreig[m]> It's an input to the fpga?
<iposthuman[m]> I just looked at the specks and it IS an output! Oops
<adamgreig[m]> Aah good good, thought I had totally forgotten about SRAM there lol
<iposthuman[m]> it controls which byte is enabled on the output. which is wierd seeing as the chip has an OE signal.
<iposthuman[m]> i guess it is for finer control of the bytes. there must be a design that would take advantage of that feature.
<galibert[m]> you sure it's not select on write?
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<iposthuman[m]> lb and ub
<iposthuman[m]> i guess this give
<iposthuman[m]> I'm assuming it is for controlling both bytes indepently on the bus
<iposthuman[m]> in my case i'm always enabling both the lower and upper bytes
<iposthuman[m]> for RISC-V this would allow byte mask addressing.
<galibert[m]> well, it's more useful on write than on read
<iposthuman[m]> Does this make any sense?
<iposthuman[m]> I think it is saying you can basically control byte updates. I agree adamgreig (@_discord_614384955182678017:catircservices.org) is more usefull on writes
<iposthuman[m]> Found it. you were right adamgreig (@_discord_614384955182678017:catircservices.org) : UB# and LB# enables a
<iposthuman[m]> byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified
<iposthuman[m]> on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location.
<galibert[m]> I'm not adam though :-)
<adamgreig[m]> Sounds about right but yea I can't take the credit for it :p
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