whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<Sarayan> Is there a guide somewhere on how to use wishbone in amaranth?
<Sarayan> I'm trying to use a minerva riscv core to control some code I want to test. The core provides two wishbone endpoints, and I need to add support (e.g. somewhere in the memory map) for some bootstrap ram, the sram and the dram of the board, my stuff, plus extra fun like sd port and serial
<Sarayan> what's the correct way to go about it?
<Sarayan> looks like I should leverage stuff from amaranth-soc?
<whitequark> yeah
<whitequark> I think Minerva had some examples of it
<Sarayan> I didn't find them, I may not have looked in the correct place
<Sarayan> and sadly opencores and its wishbone doc is down
<whitequark> oh right, I had a repo elsewhere
<whitequark> I'll find it in a bit
<antoinevg[m]> Sarayan: I found this to be helpful -> https://github.com/lambdaconcept/lambdasoc/blob/master/examples/minerva_soc.py
<Sarayan> thanks. I'll study it
<Sarayan> gonna close that repo for a start
<Sarayan> clone
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<robtaylor> It’s a quite hacky but should be helpful. Likely to @catherine has big plans around this whole area…
<Sarayan> thanks
<Sarayan> wq has probably a longer todo list than mine :-)
<koschei[m]> I’ve only skimmed ChipFlow’s docs so far, but what I’ve seen looks really exciting. I should make some time to look at it in detail before my ULX3S ships