14:17 <Sarayan> Is there a guide somewhere on how to use wishbone in amaranth?

14:19 <Sarayan> I'm trying to use a minerva riscv core to control some code I want to test. The core provides two wishbone endpoints, and I need to add support (e.g. somewhere in the memory map) for some bootstrap ram, the sram and the dram of the board, my stuff, plus extra fun like sd port and serial

14:19 <Sarayan> what's the correct way to go about it?

14:22 <Sarayan> looks like I should leverage stuff from amaranth-soc?

14:25 <whitequark> yeah

14:25 <whitequark> I think Minerva had some examples of it

14:37 <Sarayan> I didn't find them, I may not have looked in the correct place

14:38 <Sarayan> and sadly opencores and its wishbone doc is down

15:39 <whitequark> oh right, I had a repo elsewhere

15:39 <whitequark> I'll find it in a bit

16:39 <antoinevg[m]> Sarayan: I found this to be helpful -> https://github.com/lambdaconcept/lambdasoc/blob/master/examples/minerva_soc.py

16:58 <Sarayan> thanks. I'll study it

16:58 <Sarayan> gonna close that repo for a start

16:59 <Sarayan> clone

19:47 <robtaylor> Sarayan: check out https://docs.chipflow.io/en/latest/tutorial-intro-chipflow-platform.html

19:48 <robtaylor> It’s a quite hacky but should be helpful. Likely to @catherine has big plans around this whole area…

19:51 <Sarayan> thanks

19:51 <Sarayan> wq has probably a longer todo list than mine :-)

19:52 <koschei[m]> I’ve only skimmed ChipFlow’s docs so far, but what I’ve seen looks really exciting. I should make some time to look at it in detail before my ULX3S ships