<josuah>
so if I understand correctly: MyHDL dives down the bowels of python to recover the HDL syntax tree to elaborate it
<josuah>
while Amaranth has a more verbose syntax, but much more explicity, not pushing things to the python interpreter to fetch them back afterward
<josuah>
but instead lets the user model a syntax tree himself: a different way to think about HDL that might be closer to hardware than C
<josuah>
I cannot imagine how .shape() would be implemented with MyHDL methods for instance
<koschei[m]>
To be honest, I ended up really disliking HDLs that try and force an imperative execution model into a hardware description (which is much more suited to a declarative model), and I really can’t stand the strict but unstated (in syntax) divide between synthesizable and non-synthesizable constructs that a lot of HDLs have
<koschei[m]>
I’m biased though, I emailed myhdl’s author a feature request like 12 years ago and he was kinda nasty about it
<josuah>
making sure I got it right: you would prefer less barieer between synth and non-synth syntax?
<josuah>
which splits the combinational and sequential logics entirely, helping a bit for that part
<koschei[m]>
Nah honestly, I like the opposite of that — it’s pretty clear from skimming amaranth source what’s synthesizable. And the way clock domains reminds me of how Nix works in terms of declarative semantics, so that’s nice and easy for me to reason about
<koschei[m]>
(that being being a barrier between synthesizable and not — I prefer it to be very obviously demarcated)
<josuah>
and then thinking of every "if" as combining multiple signals with gates from the "current context" (totally implicit in Verilog), and making the signal coming out of it be the new context.
<josuah>
with the context that becomes a mux for the signals assignments downstream
<josuah>
so the "=" operator is very passive, represent the connections, and the "if" syntax is very constructive: actually instantiates the gates
<josuah>
the complete opposite of intuition!
<josuah>
koschei[m]: absolutely! It gives a much better grasp of what is happening. It looks more complex because it does not hide the existing "complexity"
<josuah>
the complexity of what hardware representation in software
<josuah>
MyHDL was a fun discovery though. Very readable, nice hack with the interpreter, might be pleaseant to write. But to debug though, err...
<koschei[m]>
Clash is also an interesting one, if kinda hard to understand (as Haskell DSLs are)
<koschei[m]>
I’d like to try my hand at implementing Migen-like ideas in a declarative language like Nix or Prolog one day — there are some cool advantages to each, and some really distinct disadvantages too
<josuah>
I need to give prolog a look
<josuah>
and I did not know Nix was useable outside NixOS
<josuah>
are the internals of amaranth documented anywhere perchance?
<koschei[m]>
http://www.amzi.com/AdventureInProlog/ I like this tutorial a lot, though I’d recommend switching away from Amzi Prolog and onto SWI once you finish the tutorial
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<josuah>
thanks koschei[m]
<koschei[m]>
Nix is a pretty good general purpose language for some use cases — I wouldn’t want to use it for everything, but Nix-to-source generation seems like a common one
<koschei[m]>
No problem!
<josuah>
good to know
<josuah>
this was probably what I was looking for about understanding the bowels of Amaranth:
<koschei[m]>
No problem! I also like https://github.com/lawrie/ulx4m_amaranth_examples for more practical stuff, but note that those are possibly nonworking designs for an FPGA board that doesn’t exist yet
<d1b2>
<TheZoq2> Based on your imperative execution model comment, I can't resist the urge to shamelessly plug my project https://spade-lang.org/
<koschei[m]>
That looks cool! The syntax is a bit like Rust, which I like
<koschei[m]>
Ahh and it’s implemented in Rust too, of course
<sensille>
what a cute mascot!
<d1b2>
<TheZoq2> Yep, rust is absolutely my main inspiration :)
<d1b2>
<TheZoq2> The most important metric of any language
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<_whitenotifier-9>
[amaranth-lang/amaranth-lang.github.io] whitequark eaf1c5c - Deploying to main from @ amaranth-lang/amaranth@91d45136828c55c2c035cd12ea41dd41ce1c1669 🚀