<cr1901>
Found this by chance https://github.com/PyHDI/veriloggen Looks like a lower-level take on Amaranth. At least the DSLs looks superficially similar.
<whitequark>
there's a ton of these
<whitequark>
Amaranth is not truly special in any way
<cr1901>
Well, if you decide to generate Verilog from Amaranth instead (I remember you mentioning you thought the RTLIL gen is a mistake), there's a library to do it for you :P
<whitequark>
I don't think I will go for a library though
<whitequark>
among other things, going through AST is probably not going to be fast enough for large designs