whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<alyssa> I'm trying to use Amaranth-produced Verilog with Verilator
<alyssa> Verilator's linter does not like Amaranth's implicit zero-extension, seeing errors like:
<alyssa> %Warning-WIDTH: ui_to_f16.v:63:16: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'clz' generates 5 bits.
<alyssa> 63 | assign \$43 = + clz;
<alyssa> I'm not familiar enough with Verilog to know if this is an Amaranth/Yosys bug, or Verilator is just being too pedantic.
<alyssa> passing -Wno-WIDTH to verilator makes it shut up but that seems like a hack
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<vup> I think this is mostly a lint (for handwritten verilog) and not a actual error
<vup> Oh you also might want to look at cxxrtl, depending on your goal with verilator
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<Degi> Huh, why did some accounts get banned
<lambda> they didn't, matrix bridge is just drunk again
<Degi> I see
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<lsneff> Has anyone happened to write an FFT in amaranth yet? I’m thinking of doing it for fun but don’t want to duplicate effort
<miek> yup: https://github.com/greatscottgadgets/amalthea/blob/main/amalthea/gateware/fft.py - i got sidetracked with other projects so i haven't tested on hardware yet, but it works in simulation & there are a bunch of tests for it in the root tests/ dir
<alyssa> vup: fair enough
<alyssa> Despite Amaranth not integrating with Verilator officially, Amaranth->Verilog->Verilator seemed less... experimental? then cxxrtl
<alyssa> (And Pysim would be too slow, both because of the simulation perf itself and also the overhead of generating reference vectors in Python vs C)
<alyssa> and also I wanted an excuse to learn how to use Verilator without having to write Verilog :-p
<vup> Hmm cxxsim is quite experimental. But cxxrtl not (or atleast not as much). Tbh I never used verilator, so I dont actually know how they compare, but it always looked a bit hmm more complicated I guess.
<alyssa> Oh, maybe I mixed those up
<alyssa> At any rate, I got my frankestein amaranth+verilator setup working and exhaustively tested a module in $fast, so that's nice
<alyssa> now just need to add gtest and openmp into the frankenmix :-p
<adamgreig[m]> I ended up using pytest to handle building and executing the c++ files from verilator and/or cxxrtl to avoid gtest 🙈
<alyssa> adamgreig[m]: It might be the stockholm syndrome from $DAYJOB but what's wrong with gtest? :)
<adamgreig[m]> hah, just the opposite I guess, I've used pytest so much and haven't touched gtest in a decade
<adamgreig[m]> all my tests using pysim are in pytest so it was nice to have the c++ ones be part of the same test suite
<alyssa> Fair enough :)
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<lsneff> <key2> "Lachlan Sneff: https://github...." <- Oh, that's awesome, thank you!