01:07 <_whitenotifier-e> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±2] https://github.com/YoWASP/yosys/compare/d5ff8ed932da...e6387bee21ed

01:07 <_whitenotifier-e> [YoWASP/yosys] whitequark e6387be - Update dependencies.

10:17 <cesar> Lachlan Sneff: To avoid having a signal driven by multiple modules, i'd add write ports (write enable and data) to the flag on the IRQ module interface. Then, whenever you would write to the flag in a parent module, you write to the port instead. Of course, if you just want to clear the flag externally, you don't need a full port, just a single "clear_irq" input signal.

13:53 <lsneff> cesar: I ended up doing basically that! Thanks for the suggestion though!

13:55 <lsneff> I suspect the way I did it is suboptimal though: https://github.com/lachlansneff/pio/blob/main/pio/irq.py

19:35 <lsneff> Are there examples about using GPIO in a platform-independent way? Is the `Pin` class in `amaranth.lib` the abstraction to use?

20:09 <vup> pretty much

20:09 <vup> its what you get when you 'platform.request' some resource

20:10 <vup> which is how you usually interact with IO in a platform-independent way

20:11 <vup> note that some things are not yet implemented in a platform independent manner (for example serdes)

20:30 <lsneff> vup: Awesome, thank you

23:05 <Degi> How would you even do SERDES in a platform-independent way? They seem to be so complex and have many different ways of configuring them, which I guess are very manufacturer specific (I only know ECP5 well, but I assume that other FPGAs from other manufacturers have very different SERDES architectures)

23:24 <whitequark> yeah, i don't really plan to do platform-independent SERDES as a part of Amaranth

23:35 <vup> hmm having gearing ratios as part of the request interfaces then seems a bit weird?

23:41 <whitequark> that's not SERDES, just geared I/O

23:42 <vup> whats the difference?, right now the geared I/O looks like a slim "wrapper" over the SERDES primitives to me?

23:52 <mwk> ~it doesn't come from the Serdés region of France~

23:53 <mwk> vup: fast I/O primitives generally come in two majorly different variants, for which there is varying terminology

23:54 <mwk> the SERDES referred to above is the "very fast" variant, characterized by speeds > gigabit, clock-data recovery and being ridiculously complex

23:54 <mwk> think PCI Express etc.

23:55 <mwk> the other variant is just a gearbox

23:55 <mwk> Xilinx, confusingly, calls their gearbox primitives "SERDES", and it calls the clock-data recovery thing "multi-gigabit transceivers"

23:57 <mwk> there's loads of differences between the two, but the most important one: gearbox primitives are basically a direct extension of "plain" GPIO (ie. there's usually one gearbox for every GPIO on an FPGA and you can choose to use it or not), and is simple to use (eg. just provide the slow and fast clocks and some parameters)