<cr1901>
By substituting amount=-1 in Cat(self[amount:], self[:amount])
<cr1901>
The MSB becomes the LSB
<cr1901>
that would be a rotate left
<cr1901>
And the previous LSB becomes the second bit, etc
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<SimonSapin>
Simulator.advance is documented "If there is an unstable combinatorial loop, this function will never return." Should there be a check that the graph of combinatorial Value’s is acyclic, to avoid this situation?
<SimonSapin>
wouldn’t such a cycle always be an error?
<whitequark>
perhaps, but actually implementing that is a major undertaking
<Sarayan>
whitequark: algorithmic issue or current-implementation structure issue?
<whitequark>
latter. for the same reason combinatorial loops are not detected during synthesis
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<d1b2>
<dave berkeley> Is there a way to ask a ClockDomain what its frequency is?
<whitequark>
no
<d1b2>
<dave berkeley> thanks. Another question. Would it make sense to have a PLL class : something that will work across a range of FPGA families? Litex has a system that seems to work okay.