azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
schaeg has quit [Ping timeout: 256 seconds]
Degi_ has joined ##openfpga
Degi has quit [Ping timeout: 268 seconds]
Degi_ is now known as Degi
Raito_Bezarius has quit [Ping timeout: 246 seconds]
Raito_Bezarius has joined ##openfpga
thaytan has joined ##openfpga
specing has quit [Ping timeout: 276 seconds]
emeb_mac has quit [Quit: Leaving.]
Hammdist has quit [Ping timeout: 250 seconds]
specing has joined ##openfpga
sgstair has quit [Read error: Connection reset by peer]
sgstair_ has joined ##openfpga
schaeg has joined ##openfpga
schaeg has quit [Remote host closed the connection]
schaeg has joined ##openfpga
mewt has quit [Read error: Connection reset by peer]
mewt has joined ##openfpga
schaeg has quit [Remote host closed the connection]
schaeg has joined ##openfpga
Hammdist has joined ##openfpga
emeb_mac has joined ##openfpga
<Hammdist>
so I managed to get started with the zybo board using only open source tools and a tiny bit of hacking here and there. I'm loading a quasi-FSBL through JTAG/GDB to initialize RAM and then loading u-boot, compressed bitfile, custom os kernel through JTAG and then having u-boot boot everything up. boot time is ~30 seconds now for a blinky but will
<Hammdist>
get worse as more fpga resources are used and compression supposedly becomes less effective. I think it's still somewhat better than fiddling with sdcards or netboot. not sure if there is room to bump up the JTAG speed from the default 1MHz