azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
<Hammdist> if I further understand correctly, it may be necessary to instantiate a PS7 block to get access to the required signals ... but maybe this is not supported through yosys yet
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<Hammdist> found a rather trival, but still very useful, instantiation of PS7 here: https://github.com/YosysHQ/yosys/issues/1653
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<Hammdist> managed to produce a bitfile. no axi yet, but I have a design that should blink every 2^x ticks of the PSCLK
<Hammdist> it most certainly looks like the AXI stuff is available in that PS7 block. assuming it is mapped correctly, should be possible to use
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<Hammdist> so my enthusiasm for renode was a bit short-lived. turns out it doesn't support the type of DMA required to talk to AXI efficiently on zynq-7000. it seems only to support talking to AXI via core memory accesses (there is also FastVDMA which I don't know how it's hooked up, it's probably not even through AXI at all). so I will have to wait for my
<Hammdist> board to arrive before I can start testing PS<->PL communication code
<Hoernchen_> all of this just because litex eth had issues on the colorlight/versa?
<Hammdist> no, my previous project is mostly working already on colorlight (with my own eth mac, not liteeth). still some stuff left to wrap up there, but I'm already working ahead on my next project which I'm trying to do on xilinx now (though it could be probably be done on lattice with sufficient effort and custom pcb design)
<Hoernchen_> ah