azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<Hammdist>
hi all. I'm trying to use the bram outreg mode on ecp5 with yosys. this thing is apparently the real chops when it comes to improving timings of a design. however, it seem to lack support in current yosys. there is a plug-in here that allegedly does it: https://github.com/rowanG077/yosys_ecp5_infer_bram_outreg however, when I try to use it it
<Hammdist>
complains that yosys has routed the bram outputs to LUTs, not to DFFs. manual inspection of the json confirms this to be the case. is there any way to get this working? I thought of replacing NOREG -> OUTREG in the json with sed, but that would cause simulation mismatch I'd need some matching ifdefs to in the code to keep simulation and synthesis
<Hammdist>
in sync. any better idea?
<Hammdist>
ah I got it. I was missing -no-rw-check. the plugin author did mention it in the readme, but I didn't realize that's what the LUTs were actually for.
<Hammdist>
if I understood correctly what this does, I should consider adding -no-rw-check to all my designs now, as I never rely on write-through feature of brams