azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<mwk>
so if anyone is still interested in ancient CPLDs this decade: I finally got around to writing full reverse engineered docs for XC9500 down to bitstream level, enjoy: https://prjunnamed.github.io/prjcombine/xc9500/
<mwk>
(XPLA3 and Coolrunner II docs to follow when I get bored enough)
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<Flea86>
mwk: Nice work! I've used those chips commercially in a past life :)
<Flea86>
Still have a CRII devboard somewhere
<Hammdist>
hi all. anyone knows if PS <-> PL communication is possible with nextpnr-xilinx? I imagine the xdc file would refer to some "pins" that are connected in-die to the PS ... if I manage to find out what those pins are does it have a chance to work? or does this require additional RE that has not been done?
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<Hammdist>
so I did some digging and apparently according to this https://github.com/f4pga/prjxray/issues/453#issuecomment-461733592 most of the RE is done? it's possibly not known which AXI port bits go where, but that might possibly be soluble through sufficient trial and error