azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<cyrozap>
Anyone know of any attempts to write a FOSS USB 3 device/host controller core? I was reading the USB 3 spec recently, and it seems to me that so long as an FPGA has at least one SERDES lane that can go 5 Gbps or faster, it should be able to do USB 3, so I was just wondering if anyone had actually tried it yet.
<cyrozap>
And part of the reason I was thinking about this is that TI's USB 3 PHY IC seems to be EOL, which is concerning because the only other ways to attach FPGAs over USB 3 (that I know of) is with a Cypress FX3 or FTDI's FT601, and neither of those let you interact with the lower-level parts of the USB 3 stack, like for sniffing/MitM-ing traffic.
<cyrozap>
Hoernchen: Oh, wow, that's pretty much exactly what I'm looking for. Thanks!