##openfpga on 2021-06-02 — irc logs at libera.irclog.whitequark.org

2021-05-23 22:56 azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Code: https://github.com/azonenberg/openfpga. Channel logs: https://libera.irclog.whitequark.org/##openfpga

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17:14 * promach[m] uploaded an image: (212KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/osLmEveZXuKyIWjiiozhFVSu/image.png >

17:14 <promach[m]> Something is so peculiar with the alternating {3, 0} dq bits

17:14 <promach[m]> In other words, why when ldq_w and udq_w are carrying value of 2, 4 or 6, dq carry a value of 0 ?

17:14 <promach[m]> https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L827-L828

17:14 <promach[m]> The waveform should not have value of 0 for dq signal.

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