azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<anuejn> is there a way do tell diamond that routing a clock from general routing into a pll is okay?
<anuejn> nextpnr accepts this just fine but I somehow cant convince diamond to do that
<anuejn> (on ecp5)
<tnt> Don't think so.
<tnt> (but of course ... just because I didn't find it doesn't mean there isn't one)
<anuejn> huh sad