azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<anuejn>
does anyone know if there is a difference between LVDS25E and manually driving two LVCMOS25 Pins complementary on ECP5?
<anuejn>
i.e. do the output buffers do something special?
<anuejn>
also: can I just set a 3v3 iostandard and supply 2v5 as bank voltage to work around "Trellis limitation: DRIVE can only be set on 3V3 IO pins"